Method and apparatus for sorting elements in hardware structures

A method for sorting elements stored in hardware structures, said method comprising:

• allocating elements out of order into an unordered input queue (UIQ) of a load store queue of a processor;
• selecting a plurality of elements to order from the UIQ;
• presenting each of the plurality of elements to a respective multiplexer;
• generating a select signal for a respective enabled multiplexer corresponding to each element in response to finding a match between at least one least significant bit of a respective identifier associated with said each element and a port number of an ordered retirement queue in the load store queue.

An apparatus for sorting elements stored in hardware structures, said apparatus comprising:

• a memory;
• a processor communicatively coupled to said memory, wherein said processor is configured to process instructions out of order, and further wherein said processor is configured to:
• allocate elements out of order into an unordered input queue (UIQ) of the processor;
• select a plurality of elements to order from the UIQ;
• present each of the plurality of elements to a respective multiplexer;
• generate a select signal for a respective enabled multiplexer corresponding to each element in response to finding a match between at least one least significant bit of a respective identifier associated with said each element and a port number of an ordered retirement queue of the processor.