Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer
AssigneeApple Inc.
InventorsConrado Blasco-Allue, Ian D. Kountanis
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AssigneeApple Inc.
InventorsConrado Blasco-Allue, Ian D. Kountanis
Estimating the term…
Methods, apparatuses, and processors for packing multiple iterations of a loop in a loop buffer. A loop candidate that meets the criteria for buffering is detected in the instruction stream being executed by a processor. When the loop is being written to the loop buffer and the end of the loop is detected, another iteration of the loop is written to the loop buffer if the loop buffer is not yet halfway full. In this way, short loops are written to the loop buffer multiple times to maximize the instruction operations per cycle throughput out of the loop buffer when the processor is in loop buffer mode.
An apparatus comprising:
A processor comprising:
A method comprising:
Dependencies are inferred from the claim text.
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For instruction reuse, e.g. trace cache, branch target cache: loop buffering
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
Instruction analysis, e.g. decoding, instruction word fields: of variable length instructions
For non-sequential address: for loops, e.g. loop detection or loop counter
About 7 years 6 months of term left · ends 29 Apr 2034 (estimated)
Field of the Invention
The present invention relates generally to processors, and in particular to methods and mechanisms for packing multiple iterations of a loop in a loop buffer.
Description of the Related Art
The above and further advantages of the methods and mechanisms may be better understood by referring to the following description in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates one embodiment of a portion of an integrated circuit.
FIG. 2 is a block diagram that illustrates one embodiment of a processor core.
In the following description, numerous specific details are set forth to provide a thorough understanding of the methods and mechanisms presented herein. However, one having ordinary skill in the art should recognize that the various embodiments may be practiced without these specific details. In some instances, well-known structures, components, signals, computer program instructions, and techniques have not been shown in detail to avoid obscuring the approaches described herein. It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements.
This specification includes references to “one embodiment”. The appearance of the phrase “in one embodiment” in different contexts does not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure. Furthermore, as used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include”, “including”, and “includes” mean including, but not limited to.
Terminology. The following paragraphs provide definitions and/or context for terms found in this disclosure (including the appended claims):