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AssigneeFuji Xerox Co., Ltd.
InventorsDaizo Tominaga, Takumi Kawahara, Shotaro Miyamoto
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An information processing apparatus includes a first controller that is controlled by a first operating system and a second controller that is controlled by a second operating system different from the first operating system. The first controller outputs a waiting instruction waiting persistently until a response is transmitted from a control target. The second controller converts the waiting instruction outputted from the first controller into a periodic instruction waiting periodically until a response is transmitted from the control target, and outputs the periodic instruction to the control target.
An information processing apparatus comprising:
A non-transitory computer readable medium storing a program causing a computer to execute a process for information processing, the computer including a first controller circuit that is controlled by a first operating system and a second controller circuit that is controlled by a second operating system different from the first operating system, the process comprising:
A non-transitory computer readable medium storing a program causing a computer to execute a process for information processing, the computer including a first controller circuit and a second controller circuit, the process comprising:
Dependencies are inferred from the claim text.
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Arrangements for executing specific machine instructions: to perform miscellaneous control operations, e.g. NOP
Arrangements for executing machine instructions, e.g. instruction decode: instruction operation extension or modification
Concurrent instruction execution, e.g. pipeline or look ahead: recovery, e.g. branch miss-prediction, exception handling
Task transfer initiation or dispatching: by program, e.g. task dispatcher, supervisor, operating system
About 9 years 2 months of term left · ends 7 Jan 2036 (estimated)
This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2014-096898 filed May 8, 2014.
The present invention relates to an information processing apparatus and a non-transitory computer readable medium.
According to an aspect of the invention, there is provided an information processing apparatus including a first controller that is controlled by a first operating system and a second controller that is controlled by a second operating system different from the first operating system. The first controller outputs a waiting instruction waiting persistently until a response is transmitted from a control target. The second controller converts the waiting instruction outputted from the first controller into a periodic instruction waiting periodically until a response is transmitted from the control target, and outputs the periodic instruction to the control target.
Exemplary embodiments of the present invention will be described in detail based on the following figures, wherein:
FIG. 1 is a block diagram illustrating an exemplary configuration of an information processing apparatus according to an exemplary embodiment of the present invention; and
FIG. 2 is a timing chart for describing an exemplary operation of the information processing apparatus according to the exemplary embodiment of the present invention.
FIG. 1 is a block diagram illustrating an exemplary configuration of an information processing apparatus according to an exemplary embodiment of the present invention. An information processing apparatus 1 is, for example, a loosely coupled multiprocessor system in which a first central processing unit (CPU) 20 and a second CPU 30 which operate on the basis of operating systems (OS) different from each other are connected to each other via a system bus 5.
The operating systems different from each other are a first OS 2 and a second OS 3. The first OS 2 is an OS having a real-time property lower than that of the second OS 3. The first OS 2 is an OS, for example, based on the Linux® architecture, and the second OS 3 is an OS, for example, based on the ARM® architecture.
The system bus 5 is a common path for the first CPU 20, the second CPU 30, and the like which exchange signals, information, and the like. The system bus 5 is connected to a shared memory 4 which may be accessed by the first CPU 20 and the second CPU 30. The system bus 5 is connected to a storage medium 61 and a hard disk drive (HDD) 62 via an input/output unit 60 located on the first CPU 20 side. The system bus 5 is connected to various drivers 65, 67, and 69 via an input/output unit 64 located on the second CPU 30 side. The drivers 65, 67, and 69 are connected to an operation display unit 66, an image input unit 68, and an image output unit 70, respectively. The system bus 5 is connected to a SEEPROM (serial electrically erasable programmable read only memory) 71 and a communication unit 63 for connecting the information processing apparatus 1 to a local area network (LAN) or the like. The operation display unit 66, the image input unit 68, and the image output unit 70 are exemplary devices to be controlled.