Picoengine having a hash generator with remainder input S-box nonlinearizing

A processor comprising:

• a hash generating circuit comprising:
• a modulo-2 multiplier that receives an incoming data value and receives a multiplier value and that, as a result of execution of a hash instruction, multiplies the incoming data value by the multiplier value and outputs a product value,
• wherein the product value comprises a first portion and a second portion;
• a nonlinearizing function circuit that receives a hash register value stored in a hash register and that receives a multi-bit enable signal and that outputs a programmably nonlinearized version of the hash register value (PNVHRV);
• a first modulo-2 summer that receives the first portion of the product value and that receives the PNVHRV and that outputs a first sum value;
• a modulo-2 divider that receives the first sum value and that divides the sum value by a fixed divisor value and that outputs a division remainder value;
• and
• a second modulo-2 summer that receives the division remainder value from the modulo-2 divider and that receives the second portion of the product value from the modulo-2 multiplier and that outputs a second sum value, wherein execution of the hash instruction causes the second sum value to be loaded into the hash register;
• and
• means for:
• 1) fetching the hash instruction, 2) supplying the incoming data value to the modulo-2 multiplier, 3) setting the multiplier value, and 4) supplying the multi-bit enable signal to the non-linearizing function circuit, wherein the hash register is a part of the means.

A processor comprising:

• a hash register;
• and
• a hash generating circuit comprising:
• a modulo-2 multiplier that receives an incoming data value and that, as a result of execution of a hash instruction, multiplies the incoming data value by a multiplier value and outputs a product value, wherein the product value comprises a first portion and a second portion;
• an S-box circuit that comprises a plurality of S-boxes, wherein the S-box circuit receives a hash register value stored in the hash register and outputs a programmably modified version of the hash register value;
• a first modulo-2 summer that receives the first portion of the product value and that receives the programmably modified version of the hash register value and that outputs a first sum value;
• a modulo-2 divider that receives the first sum value and that divides the sum value by a value and that outputs a division remainder value;
• and
• a second modulo-2 summer that receives the division remainder value from the modulo-2 divider and that receives the second portion of the product value from the modulo-2 multiplier and that outputs a second sum value, wherein execution of the hash instruction by the processor causes the second sum value to be loaded into the hash register.

A processor comprising:

• a hash register that stores a hash register value;
• an input data register that stores an incoming data value;
• and
• means for generating a hash value given by the modulo-2 polynomial equation:
• ((D(X)*M(X))+(PNVHRV(X)+X64)) % G(X), wherein D(X) is an incoming data value polynomial to be hashed, wherein M(X) is a multiplier value polynomial, wherein G(X) is a reducing generator polynomial, wherein PNVHRV is a programmably nonlinearized version of the hash register value, wherein +X64 denotes an operation of taking the most significant sixty-four bits, and wherein % G(X) denotes an operation of obtaining the remainder of a modulo-2 divide by G(X) and adding in that remainder value.