US 9,753,695 B2 · Datapath circuit for digital signal processors

Abstract

A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital hardware calculator for parallel computation. The digital hardware calculator and the MAC may be coupled to an input memory element for receipt of input operands. The MAC may include a digital multiplier structure with partial product generators coupled to an adder to multiply a first and second input operands and generate a multiplication result. The digital hardware calculator may include a first look-up table coupled between a calculator input and a calculator output register. The first look-up table may include table entry values mapped to corresponding math function results in accordance with a first predetermined mathematical function. The digital hardware calculator may be configured to calculate, based on the first look-up table, a computationally hard mathematical function such as a logarithm function, an exponential function, a division function and a square root function.

Claims20

Dependent claims

A processing system, comprising:

an input data register to store input operand data;
a digital multiply and accumulate (MAC) system and a calculator system each having inputs coupled to the input data register, wherein:
the MAC system comprises a multiplier stage and an adder stage;
and
the calculator system comprises a look-up table operatively coupled to the input data register, the look-up table having a plurality of entries mapped to by candidate input operand data, the entries storing corresponding pre-calculated results of a predetermined mathematical function performed on the candidate input operand data and the look-up table having an output connected to an input of the adder stage, the output configured to provide a result of the predetermined mathematical function from a table entry;
wherein the look-up table comprises a readable and writable memory storing the plurality of entries and the corresponding pre-calculated results, the readable and writeable memory supporting run-time changes to the predetermined mathematical function.

3 more elements

A method of performing a mathematical calculation involving first and second predetermined mathematical functions, the first mathematical function being a multi -bit multiplication, comprising:

wherein the multi-bit multiplication is performed by a multiply and accumulate (MAC) system and the second predetermined mathematical function is performed by a separate calculator system;
wherein the processing includes, in the calculator system:
inputting at least one operand of the second predetermined mathematical function to a look-up table that stores pre-calculated results of the second predetermined mathematical function mapped to a plurality of candidate input operands, wherein pre-calculated results represent values of the second predetermined mathematical function performed on the candidate input operands, and
outputting from the look-up table a result of the second predetermined mathematical function from a table entry mapped to by the at least one inputted operand;
and
adding the result output from the look-up table to a value obtained by the MAC system based on the multi-bit multiplication;
and
wherein the pre-calculated results of the second predetermined mathematical function are stored in a readable and writable memory, the readable and writable memory configured to support run-time changes to the second predetermined mathematical function.

5 more elements

Dependencies are inferred from the claim text.

Datapath circuit for digital signal processors

Life of this patent

Datapath circuit for digital signal processors

Life of this patent

Abstract

Claims20