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US 9,753,692 B2Granted
Multiplier pipelining optimization with a postponed estimation correction
AssigneeIntel Corporation
InventorsT. J. O'Dwyer, Pierre Laurent
Life of this patent
Estimating the term…
Abstract
One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.
Claims18
A system comprising:
- a register to store an operand, the operand initially corresponding to a multiply result;
- a multiplier;
- and
- optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred,
- the first reduction stage comprising multiplying, by the multiplier, an operand element of the multiply result and a plurality of elements of a first constant parameter, m′, and adding each product to an intermediate result to yield a reduction stage 1 result of a modified Barrett reduction,
- the second reduction stage comprising multiplying, by the multiplier, an operand element of the intermediate result and a plurality of elements of a second constant parameter, μ.
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A method comprising:
- initiating, by optimizer logic, a first reduction stage to operate on an operand, the operand initially corresponding to a multiply result;
- initiating, by the optimizer logic, a second reduction stage prior to completion of the first reduction stage;
- and
- determining, by the optimizer logic, whether a carry propagation has occurred,
- the first reduction stage comprising multiplying, by a multiplier, an operand element of the multiply result and a plurality of elements of a first constant parameter, m′, and adding each product to an intermediate result to yield a reduction stage 1 result of a modified Barrett reduction,
- the second reduction stage comprising multiplying, by the multiplier, an operand element of the intermediate result and a plurality of elements of a second constant parameter, μ.
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At least one computer readable storage device having stored thereon instructions that when executed by one or more processors result in the following operations comprising:
- initiating a first reduction stage to operate on an operand, the operand initially corresponding to a multiply result;
- initiating a second reduction stage prior to completion of the first reduction stage;
- and
- determining whether a carry propagation has occurred,
- the first reduction stage comprising multiplying, by a multiplier, an operand element of a multiply result and a plurality of elements of a first constant parameter, m′, and adding each product to an intermediate result to yield a reduction stage 1 result of a modified Barrett reduction,
- the second reduction stage comprising multiplying, by the multiplier, an operand element of the intermediate result and a plurality of elements of a second constant parameter, μ.
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Dependencies are inferred from the claim text.