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US 9,753,691 B2Granted
Method for a stage optimized high speed adder
AssigneeIntel Corporation
InventorMohammad Abdallah
Life of this patent
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Abstract
A method for fast parallel adder processing. The method includes receiving parallel inputs from a communications path, wherein each input comprises one bit, adding the inputs using a parallel structure, wherein the parallel structure is optimized to accelerate the addition by utilizing a characteristic that the inputs are one bit each, and transmitting the resulting outputs to a subsequent stage.
Claims18
A method for fast parallel adder processing, the method comprising:
- receiving parallel inputs from a communications path, wherein each input comprises one bit;
- adding the parallel inputs using a parallel structure, wherein the parallel structure is configured to accelerate the adding by utilizing a characteristic that the parallel inputs are one bit each, wherein the parallel structure comprises a first stage and a second stage, wherein the first stage comprises a four to one adder, wherein four one bit inputs are summed to produce one output comprising a three bit non-redundant result;
- and
- transmitting resulting outputs from the adding to a subsequent stage.
1 more element
A fast parallel adder circuit, the circuit comprising:
- a parallel structure for receiving parallel inputs from a communications path, wherein each input comprises one bit, wherein the parallel structure comprises a first stage and a second stage, wherein the first stage comprises a four to one adder, wherein four one bit inputs are summed to produce one output comprising a three bit non-redundant result;
- wherein the parallel structure adds the parallel inputs, and wherein the parallel structure is configured to accelerate addition by utilizing a characteristic that the parallel inputs are one bit each and to transmit resulting outputs of the addition to a subsequent stage.
A method for fast parallel adder processing, the method comprising:
- receiving parallel inputs from a communications path, wherein each input comprises one bit;
- adding the parallel inputs using a parallel structure, wherein the parallel structure is configured to accelerate the adding by utilizing a characteristic that the parallel inputs are one bit each, wherein the parallel structure comprises a first stage and a second stage, wherein the first stage comprises a four to one adder, wherein four one bit inputs are summed to produce one output comprising a three bit non-redundant result;
- and
- transmitting resulting outputs from the adding to a subsequent stage.
1 more element
Dependencies are inferred from the claim text.