US 9,753,667 B2Granted

High bandwidth memory and glitch-less differential XOR

AssigneeAvago Technologies General IP (Singapore) Pte. Ltd.

InventorsTravis Hebig, Myron Buer, Carl Monzel, Richard John Stephani

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Abstract

A high-bandwidth multiple-read memory device includes multiple memory blocks, multiple address input buses, and a number of output data buses. The memory blocks include an auxiliary memory block and each memory block include several memory sub-blocks including an auxiliary memory sub-block. The output data buses output data corresponding to addresses corresponding to the address input buses during a multiple-read operation. The addresses correspond to a single memory sub-block of the memory sub-blocks of a memory block. Also described is differential XOR circuit that includes a selection logic circuit, a precharger circuit, and a multiplexer. The selection logic circuit provides a complementary output signal corresponding to a single-ended input signal. The multiplexer provides, during an evaluate phase, a differential output signal.

Claims16

Dependent claims

A high-bandwidth multiple-read memory device, the device comprising:

a plurality of memory blocks including an auxiliary memory block, each of the plurality of memory blocks comprising a plurality of memory sub-blocks, the plurality of memory sub-blocks comprising an auxiliary memory sub-block, wherein the auxiliary memory block comprises a plurality of auxiliary memory sub-blocks, and wherein content of each auxiliary memory sub-block is based on content of at least some of the plurality of memory sub-blocks or auxiliary memory sub-blocks;
a plurality of address input buses;
and
a plurality of output data buses configured to output data corresponding to a plurality of addresses, wherein the plurality of addresses correspond to the plurality of address input buses during a multiple-read operation,
wherein the multiple-read operation comprises reading the plurality of addresses corresponding to a single memory sub-block of the plurality of memory sub-blocks of a memory block of the plurality of memory blocks by using auxiliary memory sub-blocks, the auxiliary memory block, and one or more XOR gates.

2 more elements

A method for providing a high-bandwidth multiple-read memory device, the method comprising:

partitioning a memory device into a plurality of memory blocks including an auxiliary memory block, each memory block of the plurality of memory blocks comprising a plurality of memory sub-blocks including an auxiliary memory sub-block, wherein the auxiliary memory block comprises a plurality of auxiliary memory sub-blocks, and wherein content of each auxiliary memory sub-block is based on content of at least some of the plurality of memory sub-blocks or auxiliary memory sub-blocks;
and
configuring a plurality of output data buses of the memory device to output data corresponding to a plurality of addresses corresponding to a plurality of address input buses during a multiple-read operation,
wherein
the multiple-read operation comprises reading the plurality of addresses corresponding to a single memory sub-block of the plurality of memory sub-blocks of a memory block of the plurality of memory blocks by using auxiliary memory sub-blocks, the auxiliary memory block, and one or more XOR gates.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/644,114Filed 10 Mar 2015 · us provisional application
Priority: 19 Feb 2015
Published: US 2016/0246506 A125 Aug 2016
Granted: 5 Sep 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 3/064
Organizing or formatting or addressing of data: management of blocks
G06F 3/0613
Improving I/O performance: in relation to throughput
G06F 3/0629
Making use of a particular technique: configuration or reconfiguration of storage systems
G06F 3/0644
Organizing or formatting or addressing of data: management of space entities, e.g. partitions, extents, pools