Method, apparatus, and system for energy efficiency and energy conservation including determining an optimal power state of the apparatus based on residency time of non-core domains in a power saving state

A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

• generating, in an interrupt logic of a processor, a first interrupt in response to a second domain of the processor entering a power saving state and a second interrupt in response to the second domain exiting the power saving state, wherein the processor includes a plurality of domains including a first domain and the second domain;
• initiating a counter in response to occurrence of the first interrupt and halting the counter in response to occurrence of the second interrupt;
• determining in a power management unit of the processor, an actual residency time of the second domain in the power saving state using a first value associated with initiating the counter and a second value associated with halting the counter, wherein the second value is registered in the counter in response to halting the counter;
• and
• controlling a power state of the second domain using the actual residency time.

A computer system comprising:

• a plurality of input-output devices;
• a processor including:
• a plurality of domains including a first domain including a first core and a second domain including a graphics processor;
• an interrupt generator to generate a first interrupt in response to the graphics processor of the second domain entry into a power saving state and a second interrupt in response to the graphics processor of the second domain exit from the power saving state, wherein an entity is to start a counter in response to occurrence of the first interrupt and to stop the counter in response to occurrence of the second interrupt;
• and
• a power management unit to determine an actual residency time of the graphics processor of the second domain in the power saving state based at least on a value of the counter associated with the second interrupt, wherein the power management unit is to control a power state of the graphics processor of the second domain based at least on the actual residency time of the graphics processor of the second domain in the power saving state;
• and a memory coupled to the processor.