US 9,753,524 B1Granted

Methods and apparatus for limiting a number of current changes while clock gating to manage power consumption of processor modules

AssigneeJuniper Networks, Inc.

InventorsVaishali Kulkarni, Jeffrey G. Libby, Mihir Wagh

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Abstract

A dispatch module implemented in at least one of a memory or a processing device is operatively coupled to multiple processing modules, each having a first clock configuration and a second clock configuration. The dispatch module, at a first time, changes a first processing module included in the multiple processing modules from a first clock configuration to a second clock configuration. The dispatch module prohibits, at a second time within a predetermined time period and after the first time, a second processing module included in the multiple processing modules from changing from the first clock configuration to the second clock configuration if an indicator associated with a number of changes of the multiple processing modules between a first clock configuration and a second clock configuration within the predetermined time period and prior to the second time satisfies a criterion.

Claims20

Dependent claims

A processor device, comprising:

a plurality of processor portions, each processor portion from the plurality of processor portions configured to transition from a first clock configuration to a second clock configuration in response to receiving a clock signal;
and
a dispatch processor portion, the dispatch processor portion configured to (1) send a clock signal to a processor portion from the plurality of processor portions at a first time to transition the processor portion from the plurality of processor portions from the first clock configuration to the second clock configuration and (2) increment a counter in response to sending the clock signal, the counter associated with a number of clock configuration changes during a predetermined time period,
the dispatch processor portion configured to prohibit a change in clock configuration of each processor portion from the plurality of processor portions during the predetermined time period if a value of the counter equals a threshold number of clock configuration changes during the predetermined time period, the threshold number of clock configuration changes being based on a threshold number of electric current changes for at least one of a chip package or a power supply associated with the plurality of processor portions.

1 more element

A method, comprising:

initiating, at a first time, a clock signal at a first processor portion from a plurality of processor portions;
defining a predetermined time period beginning at the first time;
incrementing a counter in response to initiating the clock signal at the first processor portion from the plurality of processor portions, the counter associated with a number of times an electric current changes during the predetermined time period as a result of initiating or gating a clock signal at a processor portion from the plurality of processor portions;
gating, at a second time and within the predetermined time period, a clock signal at a second processor portion from the plurality of processor portions;
incrementing the counter in response to gating the clock signal at the second processor portion from the plurality of processor portions;
and
prohibiting within the predetermined time period, at least one of an initiation or a gating of a clock signal at a processor portion from the plurality of processor portions when a value of the counter satisfies a criterion associated with a threshold number of changes in electric current during the predetermined time period for at least one of a chip package or a power supply associated with the plurality of processor portions.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/274,548Filed 23 Sep 2016 · continuation
Priority: 13 Mar 2013
Granted: 5 Sep 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
G06F 1/04
Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00: generating or distributing clock signals or signals derived directly therefrom
G06F 1/26
Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00: power supply means, e.g. regulation thereof
G06F 1/3225
Monitoring of peripheral devices: of memory devices