Serial peripheral interface and methods of operating same

An apparatus, comprising:

• a serial peripheral interface (SPI) including:
• a first command state machine (CSM) configured to receive/transmit data on a rising edge of a first clock signal;
• a second CSM configured to receive/transmit data on a rising edge and on a falling edge of a second clock signal;
• a clock generator configured to provide a first clock signal to the first CSM and provide a second clock signal to the second CSM;
• and
• a select generator configured to select the second CSM for command processing responsive to the SPI being simultaneously in a Double Transfer Rate (DTR) mode and a Deep Power Down (DPD) mode.

An apparatus, comprising:

• a serial peripheral interface (SPI) including:
• a first command state machine (CSM) selected to process commands while the SPI is not in both a double transfer rate (DTR) mode and a deep power down (DPD) mode, wherein the first CSM is configured to receive/transmit data on a rising edge of a clock signal;
• a second CSM coupled to the first CSM by at least one processing control passing indication signal line, the second CSM being selected to process commands while the SPI is in both the DTR mode and the DPD mode, wherein the second CSM is configured to receive/transmit data on the rising edge and on a falling edge of the clock signal;
• a clock generator coupled to the first CSM by a first clock signal line, and coupled to the second CSM by a second clock signal line;
• and
• a select generator coupled to the first CSM by a first select signal line and coupled to the second CSM by a second select signal line.

A method, comprising:

• synchronously processing commands in a serial peripheral interface (SPI) using a first command state machine (CSM) while the first CSM is able to properly process commands;
• determining that the first CSM is unable to properly process commands based an operational characteristic associated with the first CSM;
• selectively enabling, by the SPI, the second CSM based on the determination that the first CSM is unable to properly process commands;
• synchronously processing commands in the SPI using a second CSM while the first CSM is unable to properly process commands;
• and
• synchronously processing commands in the SPI using the second CSM while the SPI is in a Deep Power Down mode,
• wherein the DPD mode is a lowest power consumption state for the SPI other than a power down state and wherein the first CSM is configured to receive/transmit data on a rising edge of a clock signal and the second CSM is configured to receive/transmit data on the rising edge and on a falling edge of the clock signal.

A method, comprising:

• while a serial peripheral interface (SPI) is not in both a Double Transfer Rate (DTR) mode and a Deep Power Down (DPD) mode:
• selecting a first command state machine (CSM);
• providing a clock signal having a frequency to the first CSM while the SPI is not in the DTR mode or providing the clock signal having double the frequency to the first CSM while the SPI is in the DTR mode;
• and
• synchronously processing commands using the first CSM, wherein the first CSM is configured to receive/transmit data on a rising edge of the clock signal;
• and
• while the SPI is in both the DTR mode and the DPD mode:
• selecting a second CSM;
• providing a clock signal having the frequency to the second CSM;
• and
• synchronously processing commands using the second CSM, wherein the second CSM is configured to receive/transmit data on the rising edge and on the falling edge of the clock signal, and wherein a number of commands processed by the second CSM is less than a number of commands processed by the first CSM.