# US 9,753,474 B2 · Low-power low-dropout voltage regulators with high power supply rejection and fast settling performance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,753,474 B2 - Document ID: US9753474B2 - Status: Granted - Kind: B2 - Application number: 14/173,742 - Filed: 2014-02-05 - Published: 2015-07-16 - Granted: 2017-09-05 - Earliest claimed: 2014-01-14 - Assignees: Avago Technologies General IP (Singapore) Pte. Ltd. - Applicants: Broadcom Corporation - Inventors: Jinghua Zhang; Ricky Setiawan; Jeffrey Norwood Harrison - Web page: https://patentgrep.com/patent/US9753474B2 ## CPC - G05F 1/575: characterised by the feedback circuit - G05F 1/56: using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract A low-power low-dropout (LDO) voltage regulator device includes an error amplifier, a level-shifter circuit, and an NMOS pass transistor. The error amplifier compares a sampled portion of a regulated output voltage of the LDO voltage regulator with a reference voltage and generates an error signal. The level-shifter circuit is coupled to the error amplifier. The NMOS pass transistor provides the regulated output voltage with low dropout operation. The level-shifter circuit can shift a voltage level of the error signal to facilitate the low dropout operation of the NMOS pass transistor. ## Claims ### Claim 1 A low-power low-dropout (LDO) voltage regulator device, the device comprising: an error amplifier configured to compare a sampled portion of a regulated output voltage of the LDO voltage regulator device with a reference voltage and to generate an error signal at a single-ended output node of the error amplifier; a level-shifter circuit coupled to the error amplifier; a fast loop comprising a current mirror and a gain boosting circuit coupled to the level-shifter circuit and configured to improve a transient response-time and a slew rate of the LDO voltage regulator device; and an NMOS pass transistor configured to provide the regulated output voltage with low dropout operation, wherein the level-shifter circuit comprises a source follower including a PMOS transistor and is configured to shift a voltage level of the error signal at the single-ended output node of the error amplifier to facilitate the low dropout operation of the NMOS pass transistor, and wherein a gate terminal of the NMOS pass transistor is connected to an output node of the source follower. ### Claim 2 (depends on 1) The LDO voltage regulator device of claim 1, wherein the NMOS pass transistor is configured to achieve a high input impedance that results in a high power supply rejection (PSR) performance of the LDO voltage regulator device, wherein the high PSR comprises approximately 10 dB at 100 MHz. ### Claim 3 (depends on 1) The LDO voltage regulator device of claim 1, wherein the NMOS pass transistor is configured with a low output impedance that results in a high unity-gain-bandwidth (UGB) performance of the LDO voltage regulator device. ### Claim 4 (depends on 3) The LDO voltage regulator device of claim 3, wherein achieving the high UGB results in an improvement of more than 60% in a settling time of the LDO voltage regulator device, and wherein the settling time of the LDO voltage regulator device comprises dip-settling time and overshoot-settling time of the LDO voltage regulator device. ### Claim 5 (depends on 1) The LDO voltage regulator device of claim 1, wherein the level-shifter circuit comprises a compensation capacitor coupled between a gate terminal and a source terminal of the PMOS transistor. ### Claim 6 (depends on 5) The LDO voltage regulator device of claim 5, wherein the compensation capacitor is configured to allow low-current operation of the level-shifter circuit by cancellation of a non-dominant pole at the gate terminal of the NMOS pass transistor. ### Claim 7 (depends on 1) The LDO voltage regulator device of claim 1, wherein the fast loop further comprises a coupling capacitor that is used by the fast loop to sense a transient in the regulated output voltage, and wherein the fast loop is configured to increase a current provided to the level-shifter circuit by modification of a transient current that is generated based on the regulated output voltage. ### Claim 8 A method for providing a low-power low-dropout (LDO) voltage regulator, the method comprising: configuring an error amplifier to compare a sampled portion of a regulated output voltage of the LDO voltage regulator with a reference voltage and to generate an error signal at a single-ended output node of the error amplifier; coupling a level-shifter circuit comprising a source follower including a PMOS transistor to the error amplifier; coupling a fast loop comprising a current mirror and a gain boosting circuit to the level-shifter circuit and configuring the fast loop to improve a transient response-time and a slew rate of the LDO voltage regulator; and configuring an NMOS pass transistor to provide the regulated output voltage with low dropout operation; and configuring the level-shifter circuit to shift a voltage level of the error signal at the single-ended output node of the error amplifier to facilitate the low dropout operation of the NMOS pass transistor, wherein a gate terminal of the NMOS pass transistor is connected to an output node of the source follower. ### Claim 9 (depends on 8) The method of claim 8, wherein the fast loop further comprises a coupling capacitor that is used by the fast loop to sense a transient in the regulated output voltage, and wherein the fast loop is configured to increase a current provided to the level-shifter circuit by modification of a transient current that is generated based on the regulated output voltage. ### Claim 10 (depends on 8) The method of claim 8, further comprising configuring the NMOS pass transistor to achieve a high input impedance that results in a high power supply rejection (PSR) performance of the LDO voltage regulator, wherein the high PSR comprises approximately 10 dB at 100 MHz. ### Claim 11 (depends on 8) The method of claim 8, further comprising configuring the NMOS pass transistor with a low output impedance that results in a high unity-gain-bandwidth (UGB) performance of the LDO voltage regulator. ### Claim 12 (depends on 11) The method of claim 11, further comprising improving a settling time of the LDO voltage regulator by more than 60% by achieving the high UGB, and wherein the settling time of the LDO voltage regulator device comprises a dip-settling time and an overshoot-settling time of the LDO voltage regulator. ### Claim 13 (depends on 8) The method of claim 8, wherein coupling the level-shifter circuit comprises coupling a compensation capacitor between a gate terminal and a source terminal of the PMOS transistor. ### Claim 14 (depends on 13) The method of claim 13, further comprising configuring the compensation capacitor to allow low-current operation of the level-shifter circuit by cancellation of a non-dominant pole at the gate terminal of the NMOS pass transistor. ### Claim 15 A communication device, comprising: a low-power low-dropout (LDO) voltage regulator device comprising: an error amplifier configured to generate an error signal at a single-ended output node of the error amplifier based on a comparison between a sampled portion of a regulated output voltage of the LDO voltage regulator and a reference voltage; an NMOS pass transistor configured to provide the regulated output voltage with low dropout operation; a level-shifter circuit coupled to the error amplifier and the NMOS pass transistor and configured to shift a voltage level of the error signal at the single-ended output node of the error amplifier to facilitate the low dropout operation of the NMOS pass transistor, wherein the level-shifter circuit comprises a source follower including a PMOS transistor, and wherein a gate terminal of the NMOS pass transistor is connected to an output node of the source follower; and a fast loop comprising a current mirror and a gain boosting circuit coupled to the level-shifter circuit and configured to improve a transient response-time and a slew rate of the LDO voltage regulator device. ### Claim 16 (depends on 15) The communication device of claim 15, wherein the NMOS pass transistor is configured with a low output impedance that results in a high unity-gain-bandwidth (UGB) performance of the LDO voltage regulator device. ### Claim 17 (depends on 16) The communication device of claim 16, wherein achieving the high UGB results in an improvement of more than 60% in a settling time of the LDO voltage regulator device, and wherein the settling time comprises dip-settling time and overshoot-settling time. ### Claim 18 (depends on 15) The communication device of claim 15, wherein: the NMOS pass transistor is configured to achieve a high input impedance that results in a high power supply rejection (PSR) performance of the LDO voltage regulator device, and the high PSR comprises approximately 10 dB at 100 MHz. ### Claim 19 (depends on 15) The communication device of claim 15, wherein: the level-shifter circuit comprises a compensation capacitor coupled between a gate terminal and a source terminal of the PMOS transistor, and the compensation capacitor is configured to allow low-current operation of the level-shifter circuit by cancellation of a non-dominant pole at the gate terminal of the NMOS pass transistor. ### Claim 20 (depends on 15) The communication device of claim 15, wherein: the fast loop comprises: a coupling capacitor that is used by the fast loop to sense a transient in the regulated output voltage, and wherein the fast loop is configured to increase a current provided to the level-shifter circuit by modification of a transient current that is generated based on the regulated output voltage.