# US 9,753,373 B2 · Lithography system and semiconductor processing process

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- Number: US 9,753,373 B2
- Document ID: US9753373B2
- Status: Granted
- Kind: B2
- Application number: 14/940,108
- Filed: 2015-11-12
- Published: 2017-05-18
- Granted: 2017-09-05
- Earliest claimed: 2015-11-12
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: En-Chiuan Liou; Chia-Hung Wang
- Web page: https://patentgrep.com/patent/US9753373B2

## CPC

- G03F 7/70141: {Illumination system adjustment, e.g. adjustments during exposure or alignment during assembly of illumination system}
- G01B 11/272: {using photoelectric detection means}
- G03F 7/70633: {Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching}
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- G01B: MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS

## Abstract

A semiconductor processing method is provided and includes the following steps. A first semiconductor process is performed for a wafer to obtain plural overlay datum (x, y), wherein x and y are respectively shift values in X-direction and Y-direction. Next, A re-correct process is performed by a computer, wherein the re-correct process comprises: (a) providing an overlay tolerance value (A, B) and an original out of specification value (OOS %), wherein A and B are respectively predetermined tolerance values in X-direction and Y-direction; (b) providing at least a k value (kx, ky); (c) modifying the overlay datum (x, y) according to the k value (kx, ky) to obtain at least a revised overlay datum (x′, y′); and (d) calculating a process parameter from the revised overlay datum (x′, y′). Lastly, a second semiconductor process is performed according to the process parameter . . . . The present invention further provides a lithography system.

## Claims

### Claim 1

A semiconductor processing method, comprising:
performing a first semiconductor process for a wafer to obtain plural overlay datum (x, y), wherein x and y are respectively shift values in X-direction and Y-direction;
performing a re-correct process by a computer, comprising:
(a) providing an overlay tolerance value (A, B) and an original out of specification value (OOS %), wherein A and B are respectively predetermined tolerance values in X-direction and Y-direction;
(b) providing at least a k value (kx, ky);
(c) modifying the overlay datum (x, y) according to the k value (kx, ky) to obtain at least a revised overlay datum (x′, y′); and
(d) calculating a process parameter from the revised overlay datum (x′, y′); and
performing a second semiconductor process according to the process parameter, wherein each revised overlay datum (x′, y′) is obtained by considering a rule below:
if |x|<A′, then x′=0; or
if |y|<B′, then y′=0,
wherein A′=A/kx and B′=B/kx.

### Claim 2 (depends on 1)

The semiconductor processing method according to claim 1, wherein A is not equal to B.

### Claim 3 (depends on 1)

The semiconductor processing methods according to claim 1, wherein kx is not equal to ky.

### Claim 4 (depends on 1)

The semiconductor processing method according to claim 1, in step (c),
wherein each revised overlay datum (x′, y′) is obtained by a rule considering a revised tolerance value (A′, B′),
wherein the revised tolerance value (A′, B′) is obtained by modifying the tolerance value (A, B) according to the k value (kx, ky).

### Claim 5 (depends on 4)

The semiconductor processing method according to claim 4, wherein different k values (kx, ky) are used to obtain different revised overlay dutum.

### Claim 6 (depends on 4)

The semiconductor processing method according to claim 4, wherein each k value (kx, ky) has a linear equation relationship.

### Claim 7 (depends on 1)

The semiconductor processing method according to claim 1, wherein the first semiconductor process is a lithography process and the overlay datum is obtained by observing a plural overlay marks on the wafer.

### Claim 8 (depends on 1)

The semiconductor processing method according to claim 1, wherein the second semiconductor process is another lithography process for another wafer.

### Claim 9 (depends on 1)

The semiconductor processing method according to claim 1, wherein the second semiconductor process is an exposing process applying to said wafer in the first semiconductor process.

### Claim 10

A lithography system, comprising:
an alignment module designed to perform an aligning process to obtain a plural overlay datum (x, y) on a wafer, wherein x and y are respectively shift values in X-direction and Y-direction;
a processor designed to perform a re-correct process, comprising:
(a) providing an overlay tolerance value (A, B), wherein A and B are respectively predetermined tolerance values in the X-direction and the Y-direction;
(b) providing at least a k value (kx, ky);
(c) modifying the overlay datum (x, y) according to the k value (kx, ky) to obtain at least a revised overlay datum (x′, y′); and
(d) calculating an exposure parameter from the revised overlay datum (x′, y′); and
an exposing module designed to perform an exposing process to a resist layer according to the exposure parameter, wherein each revised overlay datum (x′, y′) is obtained by considering a rule below:
if |x|<A′, then x′=0; or
if |y|<B′, then y′=0,
wherein A′=A/kx and B′=B/kx.

### Claim 11 (depends on 10)

The lithography system according to claim 10, wherein A is not equal to B.

### Claim 12 (depends on 10)

The lithography system according to claim 10, wherein kx is not equal to ky.

### Claim 13 (depends on 10)

The lithography system according to claim 10, in step (b),
wherein each revised overlay datum (x′, y′) is obtained by a rule considering a revised tolerance value (A′, B′),
wherein the revised tolerance value (A′, B′) is obtained by modifying the tolerance value (A, B) according to the k value (kx, ky).

### Claim 14 (depends on 10)

The lithography system according to claim 10, wherein different k values (kx, ky) are used to obtain different revised overlay dutum (x′, y′).

### Claim 15 (depends on 14)

The lithography system according to claim 14, wherein each k value (kx, ky) has a linear equation relationship.

### Claim 16 (depends on 10)

The lithography system according to claim 10, in step (c),
the exposure parameter is decided by an optimized revised overlay datum having an optimized OOS % less than the original OOS %.