# US 9,753,220 B2 · System and method for optical input/output arrays

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,753,220 B2
- Document ID: US9753220B2
- Status: Granted
- Kind: B2
- Application number: 15/198,821
- Filed: 2016-06-30
- Published: 2016-12-29
- Granted: 2017-09-05
- Earliest claimed: 2014-09-02
- Assignees: Huawei Technologies Co., Ltd.
- Applicants: Huawei Technologies Co., Ltd.
- Inventors: Dritan Celo
- Web page: https://patentgrep.com/patent/US9753220B2

## CPC

- H04L 49/109: Integrated on microchip, e.g. switch-on-chip
- G02B 6/124: Geodesic lenses or integrated gratings
- G02B 6/30: for use between fibre and thin-film device
- H04B 10/801: {using optical interconnects, e.g. light coupled isolators, circuit board interconnections}
- H04L 49/10: characterised by the switching fabric construction
- H04Q 11/00: Selecting arrangements for multiplex systems (multiplex systems H04J)
- H04L 45/62: {Wavelength based (optical switching H04Q11/0062)}
- H04Q 2213/1301: Optical transmission, optical switches
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- H04B: TRANSMISSION
- H04Q: SELECTING (switches, relays, selectors H01H; wireless communication networks H04W)

## Abstract

System and method embodiments are provided for optical I/O arrays for wafer scale testing. A wafer includes a plurality of dies of PIC chips. Each die includes a plurality of first and second optical I/O elements each configured to couple to a testing probe array. A row of I/O elements includes alternating ones of the first and second optical I/O elements. Each die also includes a first waveguide and a second waveguide coupling a first one of the first and second optical I/O elements to a second one of the first and second optical I/O elements, respectively. The first and second optical I/O elements configured such that the testing probe array couples to at least some of the first optical I/O elements from a first side of the PIC chip and couples to at least some of the second optical I/O elements from a second side of the PIC chip.

## Claims

### Claim 1

A wafer, comprising:
a plurality of dies of photonic integrated circuit (PIC) chips, each die comprising:
a plurality of first optical input/output (I/O) elements and a plurality of second optical I/O elements, wherein a row of I/O elements comprises alternating ones of the first optical I/O elements and the second optical I/O elements, the first and second optical I/O elements configured to couple to a testing probe array;
a first waveguide coupling a first one of the first optical I/O elements to a second one of the first optical I/O elements; and
a second waveguide coupling a first one of the second optical I/O elements to a second one of the second optical I/O elements,
wherein a waveguide routing topology of the first and second waveguides is configured such that the testing probe array couples at least some of the first optical I/O elements from a first side of the PIC chip and the testing probe array couples at least some of the second optical I/O elements from a second side of the PIC chip.

### Claim 2 (depends on 1)

The wafer of claim 1, wherein the first and second optical I/O elements comprise surface grating couplers (SGCs).

### Claim 3 (depends on 2)

The wafer of claim 2, wherein a distance between successive first and second SGCs comprises half of a pitch for one of the first and second SGCs.

### Claim 4 (depends on 1)

The wafer of claim 1, wherein a distance between neighboring optical I/O elements is half of a distance of neighboring optical fibers in a fiber array probe.

### Claim 5 (depends on 1)

The wafer of claim 1, wherein the waveguide routing topology is configured to allow each I/O element to be connected to a corresponding optical element without use of waveguide crossings.

### Claim 6 (depends on 1)

The wafer of claim 1, wherein the waveguide routing topology is configured such that an optical feedback alignment loop does not intersect with waveguides connecting devices to the I/O elements.

### Claim 7

A wafer, comprising:
a plurality of dies, each die comprising:
a first array of on-chip optical input/output (I/O) elements;
a second array of on-chip optical I/O elements, the first and second array of on-chip optical I/O elements configured to couple to a testing probe array;
a first waveguide coupling a first one of the first array of on-chip optical I/O elements to a second one of the first array of on-chip optical I/O elements; and
a second waveguide coupling a first one of the second array of on-chip optical I/O elements to a second of the second array of on-chip optical I/O elements; and
a waveguide routing topology that provides signal feedback to facilitate automated active alignment and coupling of an optical fiber array into surface grating coupler (SGC) elements,
wherein the first array and second array are interlocking such that an I/O element in the first array is separated from another I/O element in the first array by an I/O element in the second array and such that an I/O element in the second array is separated from another I/O element in the second array by an I/O element in the first array.

### Claim 8 (depends on 7)

The wafer of claim 7, wherein the first and second optical I/O elements comprise surface grating couplers (SGCs).

### Claim 9 (depends on 8)

The wafer of claim 8, wherein a distance between successive first and second SGCs comprises half of a pitch for one of the first and second SGCs.

### Claim 10 (depends on 7)

The wafer of claim 7, wherein dies comprise a photonic chip.

### Claim 11 (depends on 10)

The wafer of claim 10, wherein the photonic chip comprises a silicon photonic chip.

### Claim 12 (depends on 10)

The wafer of claim 10, wherein the photonic chip is configured such that first optical elements couple to the first optical I/O elements from a first side of the photonic chip and second optical elements couple to the second optical I/O elements from a second side of the photonic chip.

### Claim 13 (depends on 10)

The wafer of claim 10, wherein a distance between neighboring optical I/O elements is half of a distance of neighboring optical fibers in a fiber array probe.

### Claim 14 (depends on 7)

The wafer of claim 7, further comprising a waveguide routing topology that provides signal feedback to facilitate automated active alignment and coupling of an optical fiber array into surface grating coupler (SGC) elements.

### Claim 15 (depends on 14)

The wafer of claim 14, wherein the waveguide routing topology is configured to allow each I/O element to be connected to a corresponding optical element without use of waveguide crossings.

### Claim 16 (depends on 14)

The wafer of claim 14, wherein the waveguide routing topology is configured such that an optical feedback alignment loop does not intersect with waveguides connecting devices to the I/O elements.