# US 9,753,085 B2 · Tap dual port router circuitry with gated shiftDR and clockDR

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- Number: US 9,753,085 B2
- Document ID: US9753085B2
- Status: Granted
- Kind: B2
- Application number: 15/340,507
- Filed: 2016-11-01
- Published: 2017-02-16
- Granted: 2017-09-05
- Earliest claimed: 2011-08-17
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US9753085B2

## CPC

- G01R 31/318555: {Control logic}
- G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
- G01R 31/31724: {Test controller, e.g. BIST state machine (for scan test G01R31/318555)}
- G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318508: {Board Level Test, e.g. P1500 Standard (features related to boundary scan G01R31/318533)}
- G01R 31/318513: {Test of Multi-Chip-Moduls}
- G01R 31/318597: {JTAG or boundary scan test of memory devices (other scan testing of memories G11C29/32)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

## Claims

### Claim 1

An integrated circuit comprising:
(a) a test data in lead, a test clock lead, a test mode select lead, a test data out lead, and a capture lead;
(b) a TAP state machine having a clock input coupled to the test clock lead, a mode input coupled to the test mode select lead, data register control outputs that include a ClockDR signal and a ShiftDR signal, and instruction register control outputs;
(c) an instruction register having a test data input coupled to the test data in lead, instruction register control inputs coupled to the instruction register control outputs, and instruction register outputs;
(d) data registers having test data inputs coupled to the test data in lead, data register control inputs, and instruction register control inputs coupled to the instruction register outputs; and
(e) dual port router circuitry having:
(i) first multiplexer circuitry having an input connected to the capture lead, an input connected to the ShiftDR signal, a control input connected to one of the instruction register outputs, and an output;
(ii) first gating circuitry having an input connected to the output of the multiplexer circuitry, an input connected to the control input of the first multiplexer circuitry, and a gated ShiftDR signal output coupled to a data register control input of the data registers.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 in which each of the instruction register and the data registers have a test data output, and including a second multiplexer having an input for each test data output, and an output coupled to the test data out lead.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 in which each of the instruction register and the data registers have a test data output, and the state machine has a select output, and including a second multiplexer having a select input coupled to the select output, instruction register inputs coupled to the instruction register outputs, an input for each test data output, and an output coupled to the test data out lead.

### Claim 4 (depends on 1)

The integrated circuit of claim 1 in which the dual port router circuitry includes second gating circuitry having an input connected to the ClockDR signal, an input connected to the control input of the first multiplexer circuitry, and a gated ClockDR signal output coupled to a data register control input of the data registers.