# US 9,753,084 B2 · Debug circuit, semiconductor device, and debug method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,753,084 B2 - Document ID: US9753084B2 - Status: Granted - Kind: B2 - Application number: 14/751,405 - Filed: 2015-06-26 - Published: 2016-03-24 - Granted: 2017-09-05 - Earliest claimed: 2014-09-22 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: Yutaka Tamiya - Web page: https://patentgrep.com/patent/US9753084B2 ## CPC - G01R 31/31705: {Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544)} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A debug circuit, includes: a controller to start a debugging of a circuit based on first and second code values, the first code value obtained by encoding a first sequence included in a processing sequence indicating a condition for a process of the circuit, the second code value obtained by encoding a second sequence subsequent to the first sequence, wherein the controller performs to: calculate a third code value as a current code value based on signals input and output to the circuit; output, as a fourth code value, a previous third code value that is earlier than the current code value; detect the first sequence by comparing a difference between the third code value and the fourth code value with the first code value; calculate a first expected value of the third code value; and perform the process when the third code value and the first expected value match. ## Claims ### Claim 1 A debug circuit, comprising: a first memory configured to store a program; and a processor configured to execute the program to perform operations to: store, in a second memory, a first code value which is calculated using an encoding system, which generates code values based on respective sequences corresponding to signals input to and output from a hardware circuit to be debugged, based on a first sequence, which is included in a stopping sequence indicating a condition for stopping the hardware circuit, and a second code value which is calculated using the encoding system based on a second sequence, which is included in the stopping sequence; calculate, using the encoding system, a third code value based on a third sequence; generate a fourth code value corresponding to a fourth sequence which appears earlier than the third sequence by a time length corresponding to a length of the first sequence; detect the first sequence based on a result of comparing a difference between the third code value and the fourth code value with the first code value; calculate a first expected value of the third code value at an end of the stopping sequence, based on the third code value when detecting the first sequence and the second code value; calculate, using the encoding system, a new third code value based on a new third sequence; and stop an operation on the hardware circuit when the new third code value and the first expected value match with each other to perform a debug operation of the hardware circuit. ### Claim 2 (depends on 1) The debug circuit according to claim 1, wherein the code values calculated by the encoding system change in accordance with the signals input and output to the hardware circuit. ### Claim 3 (depends on 1) The debug circuit according to claim 1, wherein the debug operation includes checking a change of a signal in the hardware circuit before a stop of the operation of the hardware. ### Claim 4 (depends on 1) The debug circuit according to claim 1, wherein the fourth code value is output from a shift register. ### Claim 5 (depends on 1) The debug circuit according to claim 1, wherein the first to fourth code values are code values having linearity. ### Claim 6 (depends on 1) The debug circuit according to claim 1, wherein the processor: stores, in the second memory, a fifth code value obtained by performing a calculation, using the encoding system, based on a fifth sequence which is included in the stopping sequence and is provided between the first sequence and the second sequence; calculates a second expected value of the third code value at an end of the fifth sequence, based on the third code value when detecting the first sequence and the fifth code value; and compares the new third code value with the second expected value. ### Claim 7 (depends on 6) The debug circuit according to claim 6, wherein the processor calculates the first expected value, when the third code value and the second expected value match with each other, and does not calculate the first expected value when the third code value and the second expected value do not match with each other. ### Claim 8 (depends on 4) The debug circuit according to claim 4, wherein the shift register outputs a plurality of fourth code values by delaying the outputting of the third code value at a plurality of stages; and the processor detects the first sequence, based on a result of comparing a difference between the third code value and one of the plurality of fourth code values with the first code value. ### Claim 9 A semiconductor device, comprising: a hardware circuit to be debugged; and a debug circuit configured to debug the hardware circuit, wherein the debug circuit includes a processor which performs, based on a program, operations to: store, in a second memory, a first code value which is calculated using an encoding system, which generates code values based on respective sequences corresponding to signals input to and output from the hardware circuit to be debugged, based on a first sequence, which is included in a stopping sequence indicating a condition for stopping the hardware circuit, and a second code value which is calculated using the encoding system based on a second sequence, which is included in the stopping sequence; calculate, using the encoding system, a third code value based on a third sequence; generate a fourth code value corresponding to a fourth sequence which appears earlier than the third sequence by a time length corresponding to a length of the first sequence; detect the first sequence based on a result of comparing a difference between the third code value and the fourth code value with the first code value; calculate a first expected value of the third code value at an end of the stopping sequence, based on the third code value when detecting the first sequence and the second code value; calculate, using the encoding system, a new third code value based on a new third sequence; and stop an operation on the hardware circuit when the new third code value and the first expected value match with each other to perform a debug operation of the hardware circuit. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein the code values calculated by the encoding system change in accordance with the signals input and output to the hardware circuit. ### Claim 11 (depends on 9) The semiconductor device according to claim 9 wherein the debug operation includes checking a change of a signal in the hardware circuit before a stop of the operation of the hardware circuit. ### Claim 12 (depends on 9) The semiconductor device according to claim 9, wherein the fourth code value is output from a shift register. ### Claim 13 (depends on 9) The semiconductor device according to claim 9, wherein the first to fourth code values are code values having linearity. ### Claim 14 (depends on 9) The semiconductor device according to claim 9, wherein the processor: stores, in the second memory, a fifth code value obtained by performing a calculation, using the encoding system, based on a fifth sequence which is included in the stopping sequence and is provided between the first sequence and the second sequence; calculates a second expected value of the third code value at an end of the fifth sequence, based on the third code value when detecting the first sequence and the fifth code value; and compares the new third code value with the second expected value. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein the processor calculates the first expected value, when the third code value and the second expected value match with each other, and does not calculate the first expected value when the third code value and the second expected value do not match with each other. ### Claim 16 (depends on 12) The semiconductor device according to claim 12, wherein the shift register outputs a plurality of fourth code values by delaying the outputting of the third code value at a plurality of stages; and the processor detects the first sequence, based on a result of comparing a difference between the third code value and one of the plurality of fourth code values with the first code value. ### Claim 17 A debug method, comprising: storing, in a second memory, a first code value which is calculated using an encoding system, which generates code values based on respective sequences corresponding to signals input to and output from a hardware circuit to be debugged, based on a first sequence, which is included in a stopping sequence indicating a condition for stopping the hardware circuit, and a second code value which is calculated using the encoding system based on a second sequence, which is included in the stopping sequence; calculating, using the encoding system, a third code value based on a third sequence; generating a fourth code value corresponding to a fourth sequence which appears earlier than the third sequence by a time length corresponding to a length of the first sequence; detecting the first sequence based on a result of comparing a difference between the third code value and the fourth code value with the first code value; calculating a first expected value of the third code value at an end of the stopping sequence, based on the third code value when detecting the first sequence and the second code value; calculating, using the encoding system, a new third code value based on a new third sequence; and stop an operation on the hardware circuit when the new third code value and the first expected value match with each other to perform a debug operation of the hardware circuit. ### Claim 18 (depends on 17) The debug method according to claim 17, further comprising: reading input and output signals held in a trace buffer when stopping the hardware circuit; and a determination is made as to whether or not the input and output signals partly or completely match the stopping sequence, and when there is no match, the hardware circuit to be debugged is released from the stopping. ### Claim 19 (depends on 17) The debug method according to claim 17, wherein the debug operation includes checking a change of a signal in the hardware circuit before a stop of the operation of the hardware circuit.