# US 9,752,224 B2 · Structure for relaxed SiGe buffers including method and apparatus for forming

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- Number: US 9,752,224 B2
- Document ID: US9752224B2
- Status: Granted
- Kind: B2
- Application number: 15/210,030
- Filed: 2016-07-14
- Published: 2017-02-09
- Granted: 2017-09-05
- Earliest claimed: 2015-08-05
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: Zhiyuan Ye; Errol Antonio C. Sanchez; Keun-Yong Ban; Xinyu Bao
- Web page: https://patentgrep.com/patent/US9752224B2

## CPC

- C23C 8/02: Pretreatment of the material to be coated (C23C8/04 takes precedence)
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3218: {Phosphides}
- H10P 14/3221: {Arsenides}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3248: {consisting of two layers}
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate having a first surface;
a group III-V interlayer formed on and in contact with the first surface, wherein the group III-V interlayer comprises a GaAsxPy material; and
a group IV buffer layer comprising silicon and germanium formed on and in contact with the group III-V interlayer, wherein the concentration of arsenic in the group III-V interlayer is directly related to the concentration of germanium in the group IV buffer layer, and wherein x and y are selected to provide a lattice mismatch of less than about 5% between the group III-V interlayer and the group IV buffer layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the germanium is present in the group IV buffer layer in a concentration of between about 30 atomic percent and about 70 atomic percent.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the concentration of arsenic in the group III-V interlayer is graded, and wherein the concentration of arsenic is greater near the group IV buffer layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the group III-V interlayer has a thickness of between about 2 nm and about 400 nm.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the group IV buffer layer has a thickness of between about 20 nm and about 200 nm.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the combined thickness of the group III-V interlayer and the group IV buffer layer is less than about 600 nm.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the group IV buffer layer is substantially parallel to the interlayer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein a lattice size of the group IV buffer layer substantially matches the lattice size of the group III-V interlayer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the group III-V interlayer and the group IV buffer layer are formed at a process temperature of less than about 650° C.

### Claim 10

A method for forming a semiconductor device, comprising:
forming a first semiconductor layer on and in contact with a surface of a substrate, wherein the first semiconductor layer comprises a GaAsxPy material; and
forming a second semiconductor layer on and in contact with the first semiconductor layer, wherein the second semiconductor layer comprises a SiGe material, and wherein the first semiconductor layer and the second semiconductor layer are formed at a process temperature of less than about 650° C., and wherein x and y are selected to provide a lattice mismatch of less than about 5% between the first semiconductor layer and the second semiconductor layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein the germanium is present in the second semiconductor layer in a concentration of between about 30 atomic percent and about 70 atomic percent.

### Claim 12 (depends on 10)

The method of claim 10, wherein a concentration of arsenic in the first semiconductor layer is directly related to the concentration of germanium in the second semiconductor layer.

### Claim 13 (depends on 10)

The method of claim 10, wherein a combined thickness of the first semiconductor layer and the second semiconductor layer is less than about 600 nm.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first semiconductor layer has a thickness of between about 2 nm and about 400 nm.