Semiconductor devices having dummy patterns and methods of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJaehan Lee, Won-Seok Jung, Kyungjoong Joo
Life of this patent
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Abstract
Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices may include a substrate with a cell region and a peripheral region, a gate stack including gates stacked on the cell region of the substrate. At least one edge portion of the gate stack may have a staircase structure. The semiconductor devices may also include a channel that extend through the gate stack and is enclosed by a memory layer and at least two dummy patterns on the substrate. The at least two dummy patterns may be spaced apart from the gate stack and may be spaced apart from each other.
Claims20
A semiconductor device, comprising:
- a substrate including a cell region and a peripheral region;
- a gate stack including a plurality of gates stacked on the cell region of the substrate, at least one edge portion of the gate stack having a staircase structure;
- a channel extending through the gate stack and being enclosed by a memory layer;
- and
- at least two dummy patterns spaced apart from the gate stack on the substrate, the at least two dummy patterns being spaced apart from each other,
- wherein the peripheral region comprises at least one transistor provided on the substrate, and
- wherein the at least two dummy patterns have substantially the same structure as the at least one transistor.
A semiconductor device, comprising:
- a substrate including a cell array region and a peripheral region;
- a gate stack provided on the cell array region of the substrate, the gate stack including a plurality of word lines which are arranged along a channel extending between at least two selection lines that are spaced apart from each other and at least one edge portion having a staircase structure;
- a bit line provided on the gate stack and electrically connected to the channel;
- at least one transistor provided on the peripheral region of the substrate and covered with an insulating layer;
- and
- at least one pair of first dummy patterns provided between the gate stack and the at least one transistor and spaced apart from each other on the substrate,
- wherein the at least one pair of first dummy patterns comprises a gate insulating layer on the substrate, a gate on the gate insulating layer, and a spacer on a side surface of the gate.
A semiconductor device comprising:
- a gate stack and a peripheral transistor on a substrate;
- a first dummy pattern between the gate stack and the peripheral transistor on the substrate;
- and
- a second dummy pattern disposed between the first dummy pattern and the peripheral transistor,
- wherein the first dummy pattern is spaced apart from the gate stack and the peripheral transistor,
- wherein the gate stack includes a staircase structure at one sidewall thereof adjacent to the first dummy pattern,
- wherein the first dummy pattern includes at least two first key patterns spaced apart from each other by a first spacing, and
- wherein the second dummy pattern includes at least two second key patterns spaced apart from each other by a second spacing that is less than the first spacing.
Dependencies are inferred from the claim text.