Systems and methods for wafer alignment
AssigneeMicron Technology, Inc.
InventorsYang Chao, Keith E. Ypma, Steve J. Strauch
Life of this patent
Estimating the term…
Abstract
Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.
Claims20
A method for aligning a wafer, the method comprising:
- performing a coarse alignment procedure by (a) estimating misalignment of the wafer based on a comparison of a set of vias fabricated on the wafer and a via template, and (b) adjusting a position of the wafer based on the estimated misalignment;
- and
- after performing the coarse alignment procedure, performing a fine alignment procedure by (a) determining a center location of individual vias of the set of vias fabricated on the wafer, (b) averaging the center locations of the individual vias together to obtain an average center location of the set of vias, (c) comparing the average center location with a reference location, and (d) adjusting the position of the wafer based on the averaged center location comparison if the average center location is not within a described distance of the reference location.
A method for aligning a wafer, the method comprising:
- determining a center location of individual vias of a set of vias fabricated on the wafer;
- averaging the center locations of the individual vias together to obtain an average center location of the set of vias;
- comparing the average center location with a reference location;
- and
- adjusting a position of the wafer based on the comparison if the average center location is not within a prescribed distance of the reference location.
A non-transitory computer-readable storage medium containing instructions that, when executed by one or more processors, perform a method for aligning a wafer, the method comprising:
- receiving digital imaging data of a set of vias fabricated on the wafer;
- determining center locations of individual vias on the set of vias using the digital imaging data;
- averaging the center locations of the individual vias on the set of vias to obtain an average center location;
- comparing the average center location with a reference location;
- and
- transmitting instructions to adjust or not adjust a position of the wafer based on the comparison between the average center location and the reference location.
A system for aligning a wafer, the system comprising:
- an illumination source;
- a substrate support configured to hold the wafer;
- a controller configured to move the substrate support;
- the controller comprising a processor coupled to a memory, the memory storing instructions that, when executed by the processor, cause the system to:
- determine center locations of individual vias of a set of vias fabricated on a wafer;
- average the center locations of the individual vias together to obtain an average center location of the set of vias;
- compare the average center location with a reference location;
- and
- adjust a position of the wafer based on the comparison if the average center location is not within a prescribed distance of the reference location.
A method for aligning a wafer, the method comprising:
- determining an offset of an average center location of a set of vias fabricated on the wafer with a reference center location of a via alignment template associated with the wafer, wherein the average center location of the set of vias is based on center locations of the individual vias in the set of vias;
- and
- aligning the wafer by moving a substrate support carrying the wafer based on the determined offset.
Dependencies are inferred from the claim text.