Pipelined cascaded digital signal processing structures and methods
AssigneeAltera Corporation
InventorMartin Langhammer
Life of this patent
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Abstract
Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.
Claims11
Circuitry operating under a floating-point mode or a fixed-point mode, said circuitry comprising:
- a first circuit accepting a first data input and generating a first data output, the first circuit including:
- a first arithmetic element accepting the first data input,
- a plurality of pipeline registers disposed in connection with the first arithmetic element, and
- a cascade register that outputs the first data output;
- and
- a second circuit accepting a second data input and generating a second data output, wherein:
- the second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register, and
- the cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.
A method of operating cascaded circuitry, comprising:
- receiving, via a plurality of input registers within a first circuit, a data input signal, wherein
- the first circuit includes:
- a first arithmetic element that supports floating-point operation,
- a plurality of pipeline registers that pipeline an operation of the first arithmetic element, and
- a cascade register that is connected to a second circuit;
- receiving, from a processor, a first command signal to use the cascade register;
- and
- in response to the first command signal:
- selectively bypassing an input register from the plurality of input registers, or a pipeline register from the plurality of pipeline registers to compensate for a delay from the cascade register, and
- transmitting, via the cascade register, an interblock data signal from the first circuit to the second circuit.
Dependencies are inferred from the claim text.