Apparatus for offset correction in electronic circuitry and associated methods
AssigneeSilicon Laboratories Inc.
InventorsGang Yuan, Shouli Yan, Matthew Powell
Life of this patent
Estimating the term…
Abstract
An apparatus includes a first field effect transistor (FET) that has a body and is coupled in a circuit. The apparatus also includes a second FET that has a body and is coupled in the circuit. The circuit has an offset because of a mismatch. The apparatus further includes an offset correction circuit coupled to the body of the first FET and to the body of the second FET. The offset correction circuit provides a first offset correction signal to the body of the first FET and provides a second offset correction signal to the body of the second FET.
Claims20
An apparatus comprising:
- a first field effect transistor (FET) coupled in a circuit, the first FET having a body;
- a second FET coupled in the circuit, the second FET having a body, wherein the circuit has an offset because of a mismatch;
- and
- an offset correction circuit coupled to the body of the first FET and to the body of the second FET to provide a first offset correction signal to the body of the first FET and a second offset correction signal to the body of the second FET, wherein the offset correction circuit comprises a third FET and a fourth FET coupled in a source follower configuration.
An electronic apparatus comprising:
- a first differential amplifier including a first transistor and a second transistor, the first transistor having a body, and the second transistor having a body, wherein electrical characteristics of the first transistor differ from electrical characteristics of the second transistor;
- and
- a first offset correction circuit, comprising:
- a first current source;
- third and fourth transistors coupled to the first current source;
- and
- a first network of a set of switches and a set of resistors coupled to the third and fourth transistors to provide first and second offset correction signals to the body of the first transistor and to the body of the second transistor, respectively.
A method of correcting an offset in a circuit including first and second field effect transistors (FETs), wherein the circuit has an offset because of a mismatch, the method comprising:
- generating a first offset correction signal by using third and fourth FETs coupled in a source follower configuration;
- generating a second offset correction signal by using the third and fourth FETs;
- applying the first offset correction signal to a body of the first FET;
- and
- applying the second offset correction signal to a body of the second FET.
Dependencies are inferred from the claim text.