On-chip clock controller

A method of reducing glitches at an on-chip clock controller circuit, the method comprising:

• generating a first output clock signal at a primary clock gating cell of the on-chip clock controller circuit, the first output clock signal generated based at least in part on an input clock signal and an enable signal;
• generating a second output clock signal at a secondary clock gating cell of the on-chip clock controller circuit, the second output clock signal generated based at least in part on the input clock signal, wherein the enable signal is based at least in part on the second output clock signal, and wherein the input clock signal bypasses multiplexer operations at the on-chip clock controller circuit to reduce glitches at the on-chip clock controller circuit;
• and
• generating a data signal at a shift register of the on-chip clock controller circuit, the data signal generated based at least in part on the first output clock signal.

A non-transitory computer-readable medium comprising instructions for reducing glitches at an on-chip clock controller circuit, the instructions, when executed by a processor, cause the processor to perform operations comprising:

• generating a first output clock signal at a primary clock gating cell of the on-chip clock controller circuit, the first output clock signal generated based at least in part on an input clock signal and an enable signal;
• generating a second output clock signal at a secondary clock gating cell of the on-chip clock controller circuit, the second output clock signal generated based at least in part on the input clock signal, wherein the enable signal is based at least in part on the second output clock signal, and wherein the input clock signal bypasses multiplexer operations at the on-chip clock controller circuit to reduce glitches at the on-chip clock controller circuit;
• and
• generating a data signal at a shift register of the on-chip clock controller circuit, the data signal generated based at least in part on the first output clock signal.

An on-chip clock controller circuit comprising:

• means for generating a first output clock signal, the means for generating the first output clock signal comprising:
• a first clock input terminal coupled to receive an input clock signal;
• a first enable input terminal coupled to receive an enable signal;
• and
• a first clock output terminal configured to generate the first output clock signal based at least in part on the input clock signal and the enable signal;
• means for generating a second output clock signal, the means for generating the second output clock signal comprising:
• a second clock input terminal coupled to receive the input clock signal;
• and
• a second clock output terminal configured to generate the second output clock signal based at least in part on the input clock signal, wherein the enable signal is based at least in part on the second output clock signal;
• and
• means for generating a data signal, the data signal generated based at least in part on the first output clock signal.