Method and apparatus for converting from floating point to integer representation

An apparatus for generating a representation, in two's complement format, of an input integer A having K bits, the apparatus comprising:

• first level circuitry comprising:
• a first zero-stage circuit configured to receive a sign bit and a least significant bit A(0) of the input integer, the first zero-stage circuit configured to generate a zero-stage least-significant-bit propagate output P0(0) and a zero-stage least-significant-bit generate output G0(0) according to:
• P0(0)=A(0);
• G0(0)=inv(A(0))AND sign,
• wherein inv( ) corresponds to a logical inversion operation, AND corresponds to a logical AND operation, and sign corresponds to a logical value of the sign bit;
• and
• for whole number values of i indexed from 1 to K−1, inclusive, a further zero-stage circuit configured to receive the sign bit and a bit A(i) of the input integer other than A(0), the further zero-stage circuit configured to generate a zero-stage propagate output P0(i) according to:
• P0(i)=A(i)XOR sign,
• wherein XOR corresponds to a logical XOR operation;
• second level circuitry comprising a number of stages indexed by r, wherein r assumes whole number values between 1 and log2(K) inclusive, wherein each rth stage of the number of stages comprises a number of components indexed by i, wherein i assumes whole number values between 0 and K−1 inclusive, and wherein each of the number of components is configured to generate an ith component of an rth stage generate output Gr(i) and an ith component of an rth stage propagate output Pr(i) according to:
• for i ranging from 0 to 2r−1−1, inclusive:
• Pr(i)=Pr−1(i)
• Gr(i)=Gr−1(i);
• and
• for i ranging from 2r−1 to K−1, inclusive:
• Pr(i)=Pr−1(i)AND Pr−1(i−2r−1)
• Gr(i)=Pr−1(i)AND Gr−1(i−2r−1);
• and
• third level circuitry configured to generate a least significant bit OUT(0) of the representation, the least significant bit equal to the least significant bit A(0) of the input integer, the third level further configured to generate a number of further bits OUT(i), for i assuming whole number values between 1 and K−1, inclusive, of the representation according to:
• OUT(i)=GMAX_ROW(i−1)XOR P0(i),
• wherein MAX_ROW equals log2(K).

A method for conversion of a floating point representation to a signed integer representation, the floating point representation including a sign, an exponent, and a mantissa, the method comprising:

• a shift conditioning operation, performed by shift conditioning circuitry, the shift conditioning operation including generating a shift control signal based at least in part on the exponent;
• a two's complement operation, performed by two's complement circuitry, the two's complement operation operating at least partially concurrently with the shift conditioning operation, the two's complement operation including generating a pre-shift output, the pre-shift output corresponding to a representation, in two's complement format, of the sign and the mantissa;
• and
• a shift execution operation, performed by shift execution circuitry, the shift execution operation including shifting of the pre-shift output by a number of bit positions specified at least in part by the shift control signal;
• wherein the shift execution operation generates the signed integer representation under a predefined condition;
• wherein the exponent is expressed using E bits, and wherein the shift conditioning operation generates the shift control signal based on a scaling factor input and an exponent bias value, the exponent bias value equal to 2E−1−1, the shift conditioning operation comprising:
• inverting a most significant bit of the exponent to provide a modified exponent value, the modified exponent value corresponding to the exponent having the most significant bit thereof inverted;
• and
• receiving the scaling factor input and the modified exponent value as summands along with a carry input of logical ‘1’ and providing the shift control signal as output corresponding to a sum of the scaling factor input, the modified exponent value, and the carry input.

A method for generating a representation, in two's complement format, of an input integer A having K bits, the method comprising:

• first level operations, performed by first level circuitry, the first level operations comprising:
• a first zero-stage operation performed on a sign bit and a least significant bit A(0) of the input integer, the first zero-stage operation including generating a zero-stage least-significant-bit propagate output P0(0) and a zero-stage least-significant-bit generate output G0(0) according to:
• P0(0)=A(0);
• G0(0)=inv(A(0))AND sign,
• wherein inv( ) corresponds to a logical inversion operation, AND corresponds to a logical AND operation, and sign corresponds to a logical value of the sign bit;
• and
• for whole number values of i indexed from 1 to K−1, inclusive, a further zero-stage operation performed on the sign bit and a bit A(i) of the input integer other than A(0), the further zero-stage operation including generating a zero-stage propagate output P0(i) according to:
• P0(i)=A(i)XOR sign,
• wherein XOR corresponds to a logical XOR operation;
• second level operations, performed by second level circuitry, the second level operations comprising a number of stages indexed by r, wherein r assumes whole number values between 1 and log2(K) inclusive, wherein each rth stage of the number of stages comprises a number of component operations indexed by i, wherein i assumes whole number values between 0 and K−1 inclusive, and wherein each of the number of component operations includes generating an ith component of an rth stage generate output Gr(i) and an ith component of an rth stage propagate output Pr(i) according to:
• for i ranging from 0 to 2r−1−1, inclusive:
• Pr(i)=Pr−1(i)
• Gr(i)=Gr−1(i);
• and
• for i ranging from 2r−1 to K−1, inclusive:
• Pr(i)=Pr−1(i)AND Pr−1(i−2r−1),
• Gr(i)=Pr−1(i)AND Gr−1(i−2r−1);
• and
• third level operations, performed by third level circuitry, the third level operations comprising generating a least significant bit OUT(0) of the representation, the least significant bit equal to the least significant bit A(0) of the input integer, the third level further including generating a number of further bits OUT(i), for i assuming whole number values between 1 and K−1, inclusive, of the representation according to:
• OUT(i)=GMAX_ROW(i−1)XOR P0(i),
• wherein MAX_ROW equals log2(K).