Axially and centrally symmetric current source array
AssigneeVia Alliance Semiconductor Co., Ltd.
InventorsJade Deng, Keith Ma
Life of this patent
Estimating the term…
Abstract
A current source device having a current source array includes a plurality of current source units, a plurality of least significant bits, and a plurality of most significant bits. The current source units are arranged along a plurality rows and columns of a current source array. Each of the least significant bits includes a first amount of current source units is placed at the geometric center of the current source array. Each of the most significant bits includes a second amount of current source units. The second amount is the first amount multiplied by a positive integer. The two adjacent bits in the most significant bits are centrally symmetrical to the geometric center.
Claims8
A current source device, having a current source array, comprising:
- a plurality of current source units, arranged along a plurality of rows and a plurality of columns of the current source array;
- a plurality of least significant bits, wherein each of the least significant bits comprises a first amount of current source units, and the least significant bits are placed at a geometric center of the current source array;
- and
- a plurality of most significant bits, wherein each of the most significant bits comprises a second amount of current source units, wherein the second amount is the first amount multiplied by a positive integer, wherein two adjacent bits in the most significant bits are centrally symmetric to the geometric center;
- wherein the current source array comprises a first symmetry axis through the geometric center, each of the most significant bits is divided into two parts, and the two parts are symmetric to the first symmetry axis,
- wherein the current source array further comprises a second symmetry axis through the geometric center, wherein the second symmetry axis is orthogonal to the first symmetry axis and divides the current source array into a first region and a second region, wherein one of the two adjacent bits in the most significant bits is placed in one of the first region and the second region, and the other of the two adjacent bits in the most significant bits is placed in the other of the first region and the second region,
- wherein every most significant bit is configured with 16 current source units, a most significant bit and next most significant bit are each divided into two parts, and the two parts of a most significant bit are placed in the first region, symmetrically disposed across the first symmetry axis, and the two parts of next most significant bit are placed in the second region, symmetrically disposed across the first symmetry axis, and
- wherein the least significant bits are enclosed by the most significant bits.
Dependencies are inferred from the claim text.