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US 9,704,863 B1Granted
Forming a hybrid channel nanosheet semiconductor structure
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Peng Xu
Life of this patent
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Abstract
A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner spacer of a first material and a second nanosheet FET structure having second inner spacer of a second material. The first material is different than the second material.
Claims20
A method for fabricating a nanosheet semiconductor structure, the method comprising:
- forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having a second inner spacer comprised of a second material;
- wherein the first material is different than the second material;
- and
- wherein forming the first nanosheet FET structure and the second nanosheet FET structure comprises:
- creating a first inner spacer formation within a first silicon germanium (SiGe) channel comprised in a first channel region of a first FET region and a second inner spacer formation within a second SiGe channel comprised in a second channel region of a second FET region, wherein the first SiGe channel is formed from one or more first SiGe nanosheets and the second SiGe channel is formed from one or more second SiGe nanosheets;
- depositing a first sacrificial liner on the first FET region and a second sacrificial liner on the second FET region;
- forming a mask on the second sacrificial liner;
- forming a first source/drain region along a first silicon (Si) channel of the first channel region, wherein the first Si channel is formed from one or more first Si nanosheets;
- removing the mask and the first and second sacrificial liners;
- creating a third inner spacer formation within a second Si channel comprised in the second channel region, wherein the second Si channel is formed from one or more second Si nanosheets;
- forming a second source/drain region along the second SiGe channel;
- filling the first source/drain region with a first oxide and the second source/drain region with a second oxide;
- replacing a first gate of the first FET region with a first metal and the first SiGe channel with a first work function metal;
- and
- replacing a second gate of the second FET region with a second metal and the second Si channel with a second work function metal.
12 more elements
Dependencies are inferred from the claim text.