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US 9,704,819 B1Granted
Three dimensional fully molded power electronics module having a plurality of spacers for high power applications
AssigneeHong Kong Applied Science and Technology Research Institute Company Limited
InventorsZiyang Gao, Ya Lv
Life of this patent
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Abstract
A power electronic package includes a first substrate, a second substrate oppositely disposed from the first substrate, one or more chips disposed between the substrates, and at least three spacers. The spacers control a height variation of the power electronic package and protect the chips and other electronics from experiencing excessive stress. The height of the spacers is determined based on a height of the chips, on a height of solder blocks that connect the chips to the top substrate, and on a height of solder blocks that connect the chips to the bottom substrate.
Claims20
A power electronic package, comprising:
- a first substrate having a patterned inner surface that includes a first conductive region;
- a second substrate oppositely disposed from the first substrate and having a patterned inner surface that includes a second conductive region;
- a plurality of chips sandwiched between the first substrate and the second substrate and each of the chips having a top surface and a bottom surface;
- a first plurality of solder blocks disposed between the top surface of the chips and the first conductive region of the first substrate;
- a second plurality of solder blocks disposed between the bottom surface of the chips and the second conductive region of the second substrate;
- and
- at least three spacers each having a first end that contacts the first substrate, a second end that contacts the second substrate, and a height that is based on a height of the chips, on a height of the first plurality of solder blocks, and on a height of the second plurality of solder blocks such that the height variation of the power electronic package is controlled by the spacers;
- wherein the first substrate includes a ceramic layer sandwiched between two electrically conductive layers and the second substrate includes a ceramic layer sandwiched between two electrically conductive layers.
5 more elements
A fully molded power electronic module, comprising:
- a first direct bonded copper (DBC) substrate;
- a second DBC substrate oppositely disposed from the first DBC substrate;
- a plurality of chips sandwiched between the first DBC substrate and the second DBC substrate and each of the chips having a top surface and a bottom surface;
- a first plurality of solder blocks disposed between the top surface of the chips and the first DBC substrate;
- a second plurality of solder blocks disposed between the bottom surface of the chips and the second DBC substrate;
- and
- four spacers each having a first end that contacts the first DBC substrate, a second end that contacts the second DBC substrate, and a height that is equal to a height of one of the chips plus a height of one of the first plurality of solder blocks plus a height of one of the second plurality of solder blocks such that the spacers divert load from the chips to the spacers.
4 more elements
A method of fabricating a power electronic package, comprising:
- providing a first direct bonded copper (DBC) substrate having an electrically non-conductive region and an electrically conductive region;
- providing a second DBC substrate having a first solder base that holds a first chip, having a second solder base that holds a second chip, having an electrically non-conductive region and an electrically conductive region;
- determining, by analyzing thermal properties and reliability performance of the first and second DBC substrates and the first chip, a thickness of the first solder base and a thickness of a first solder block disposed between the first chip and the first DBC substrate;
- calculating a first height by adding the thickness of the first solder base together with a thickness of the first chip and the thickness of the first solder block;
- determining, by analyzing thermal properties and reliability performance of the first and second DBC substrates and the second chip, a thickness of the second solder base and a thickness of a second solder block disposed between the second chip and the first DBC substrate;
- calculating a second height by adding the thickness of the second solder base together with a thickness of the second chip and the thickness of the second solder block;
- determining an optimized height by taking an average of the first height and the second height when a difference between the first height and the second height is less than 0.1 mm;
- and
- mounting, between the first and second DBC substrates, at least three spacers that have a height equal to the optimized height.
6 more elements
Dependencies are inferred from the claim text.