Partially and fully parallel normaliser
AssigneeImagination Technologies Limited
InventorTheo Alan Drane
Life of this patent
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Abstract
Hardware logic arranged to normalize (or renormalize) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalization block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.
Claims10
An apparatus comprising hardware logic arranged to normalise an input n-bit binary number, the hardware logic comprising:
- a leading zero counter arranged to compute a number of leading zeros in the n-bit number;
- and
- left shifting logic arranged to perform left shifting of the n-bit number,
- wherein at least a portion of the left shifting is performed in parallel with the computing of the number of leading zeros and without input from the leading zero counter.
A method of normalising an input n-bit binary number, the method comprising:
- computing, by hardware logic a number of leading zeros in the n-bit number in a leading zero counter;
- and
- left shifting the n-bit number in left shifting hardware logic, wherein at least a portion of the left shifting is performed in parallel with the computing of the number of leading zeros and without input from the number of leading zeros computation.
A non-transitory computer readable storage medium having stored thereon computer executable program code that when executed causes at least one processor to compute a number of leading zeros in the n-bit number in a leading zero counter;
- and
- left shift the n-bit number, wherein at least a portion of the left shifting is performed in parallel with the computing of the number of leading zeros and without input from the number of leading zeros computation.
A non-transitory computer readable storage medium having stored thereon computer executable program code that, when executed at a computer system for generating a representation of a digital circuit from definitions of circuit elements and data defining rules for combining those circuit elements, cause the computer system to generate hardware logic arranged to normalise an input n-bit binary number, the hardware logic comprising:
- a leading zero counter arranged to compute a number of leading zeros in the n-bit number;
- and
- normalisation logic arranged to perform left shifting of the n-bit number, wherein at least a portion of the left shifting is performed in parallel with the computing of the number of leading zeros and without input from the leading zero counter.
Dependencies are inferred from the claim text.