US 9,697,874 B1 · Monolithic memory comprising 1T1R code memory and 1TnR storage class memory

Abstract

Providing for a monolithic memory device comprising a combination of a one-transistor, one-resistor (1T1R) memory array, and a one-transistor, multiple-resistor (1TnR, where n is a suitable integer greater than 1) memory array is described herein. By way of example, the monolithic memory device can be a stand-alone device, configured to perform functions in response to predetermined conditions and generate an output(s), or can be a removable device that can be connected to and operable with another device. In various embodiments, the 1TnR array having high memory density can serve as storage class memory (SCM) for the monolithic memory device, and the 1T1R array having high performance and efficacy can serve as code memory. In addition to the foregoing, the 1T1R array and the 1TnR array can be fabricated from at least one common layer or a common processing step, to simplify and lower cost of fabricating disclosed memory devices.

Claims40

Dependent claims

An integrated circuit, comprising:

a substrate comprising a plurality of metal oxide semiconductor (MOS) devices formed at least in part within the substrate;
a set of layers overlying the substrate and the MOS devices and facilitating electrical interconnection of two or more of the plurality of MOS devices, the set of layers comprising at least two layers;
a first array of two-terminal memory devices formed among a first subset of the set of layers, wherein the first array of two-terminal memory devices is formed in a one-transistor, multiple-resistor (1TnR, where n is an integer greater than 1) array architecture;
and
a second array of two-terminal memory devices formed among a second subset of the set of layers, wherein the second array of two-terminal memory devices is formed in a one-transistor, one-resistor (1T1R) array architecture, and wherein the first array of two-terminal memory devices and the second array of two-terminal memory devices share a common layer.

2 more elements

A memory apparatus, comprising:

a substrate having a plurality of metal oxide semiconductor (MOS) devices formed therein;
a first set of backend memory layers, comprising at least a first subset of the backend memory layers and a second subset of the backend memory layers;
a one-transistor, one-resistor (1T1R) resistive memory cell array formed within the first subset of the backend memory layers at least in part from the first set of backend memory layers;
a one-transistor, multiple-resistor (1TnR, where n is an integer greater than 1) resistive memory cell array formed within the second subset of the backend memory layers at least in part from the first set of backend memory layers;
a first set of interconnects coupling the 1T1R resistive memory cell array to a first of the plurality of MOS devices formed in the substrate;
and
a second set of interconnects connecting the 1TnR resistive memory cell array to a second of the plurality of MOS devices formed in the substrate, wherein the 1T1R resistive memory cell array and the 1TnR resistive memory cell array are fabricated in part from at least one common layer of the first set of backend memory layers.

4 more elements

Dependencies are inferred from the claim text.

Monolithic memory comprising 1T1R code memory and 1TnR storage class memory

Life of this patent

Monolithic memory comprising 1T1R code memory and 1TnR storage class memory

Life of this patent

Abstract

Claims40