Decision feedback equalizers and operating methods thereof

A signal receiving circuit comprising:

• an amplifier configured to receive an input signal, and to output an amplified input signal;
• and
• a decision feedback equalizer (DFE) configured to receive the amplified input signal, the DFE comprising:
• a sampler configured to receive the amplified input signal and to compare an amplitude of the amplified input signal with a first voltage and a second voltage;
• a DFE logic circuit configured to receive at least one first sign signal based on comparison results from the sampler, and to selectively update a tap coefficient based on the at least one first sign signal;
• a latch configured to latch an input sign signal with an input data signal, and to output at least one latched data signal and a latched sign signal, the input sign signal being based on the comparison from the sampler;
• and
• a multiplier coupled to the latch, wherein
• a first latched data signal of the at least one latched data signal is configured to be fed back to the multiplier,
• the DFE logic circuit is configured to update the tap coefficient when the at least one first sign signal indicates the amplitude of the amplified input signal is not between the first voltage and the second voltage, and
• the DFE logic circuit is configured to maintain the tap coefficient when the at least one first sign signal indicates the amplitude of the amplified input signal is between the first voltage and the second voltage.

A method for updating a tap coefficient of a decision feedback equalizer (DFE), the method comprising:

• determining a difference, using a sampler, between an amplitude of an input signal and a first predetermined voltage level and a difference between the amplitude of the input signal and a second predetermined voltage level;
• latching, by a latch, an input sign signal with an input data signal, the input sign signal being based on the determined differences;
• outputting at least one latched data signal and a latched sign signal;
• feeding a first latched data signal of the at least one latched data signal back to a multiplier;
• updating a tap coefficient, by a DFE logic circuit, when the amplitude of the input signal is not between the first predetermined voltage level and the second predetermined voltage level;
• and
• maintaining the tap coefficient when the amplitude of the input signal is between the first predetermined voltage level and the second predetermined voltage level.