Method, apparatus, system for centering in a high performance interconnect

An interconnected system, comprising:

• a first agent;
• a second agent;
• and
• an interconnect to communicatively couple the first agent to the second agent, comprising:
• a clock generator to generate a clock signal at a low speed for the interconnect;
• a phase shifter to phase shift the clock signal by a test phase;
• an error rate detector to measure an error rate of the test phase;
• the phase shifter is further to shift the clock signal by a second test phase;
• the error rate detector is further to measure an error of the second test phase;
• an error comparator to compare the error rate of the first test phase to the error rate of the second test phase and to select an optimal test phase;
• an operational phase selector to select an operational phase of the clock signal based at least in part on the optimal test phase;
• a reference voltage shifter to shift a reference voltage by a test voltage;
• the error rate detector is further to measure an error rate of the test voltage at an operational speed for the interconnect;
• and
• an operational voltage selector to select an operational reference voltage of the clock signal based at least in part on the error rate of the test voltage.

One or more tangible, non-transitory computer-readable mediums having stored thereon executable instructions to:

• generate a clock signal;
• phase shift the clock signal by a quantized test phase at a low speed for an interconnect;
• detect an error rate of the test phase;
• shift the clock signal by a second test phase;
• measure an error of the second test phase;
• compare the error rate of the first test phase to the error rate of the second test phase and select an optimal test phase;
• select an operational phase of the clock signal based at least in part on the optimal test phase;
• shift a reference voltage by a test voltage;
• measure an error rate of the test voltage at an operational speed for the interconnect;
• and
• select an operational reference voltage of the clock signal based at least in part on the error rate of the test voltage.

A method of performing interconnect centering, comprising:

• generating a clock signal at a low speed for the interconnect;
• phase shifting the clock signal by a quantized first test phase;
• detecting an error rate of the first test phase;
• shifting the clock signal by a quantized second test phase;
• measuring an error of the second test phase;
• comparing the error rate of the first test phase to the error rate of the second test phase to select an optimal test phase;
• selecting an operational phase of the clock signal based at least in part on the optimal test phase;
• shifting a reference voltage of the clock signal by a first quantized test voltage;
• measuring an error rate of the first test voltage at an operational speed for the interconnect;
• shifting the reference voltage by a quantized second test voltage;
• comparing the error rate of the first test voltage to an error rate of the second test voltage to select an optimal test voltage;
• and
• selecting an operational voltage of the clock signal based at least in part on the optimal test voltage.