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US 9,691,768 B2Granted
Nanowire or 2D material strips interconnects in an integrated circuit cell
AssigneeSynopsys, Inc.
InventorsVictor Moroz, Jamil Kawa
Life of this patent
Estimating the term…
Abstract
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or 2D material strips arranged in parallel. An integrated circuit including the circuit is described.
Claims24
A circuit, comprising:
- a first transistor;
- a second transistor;
- an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or one or more 2D material strips arranged in parallel;
- and
- patterned conductors including nanowires or 2D material strips, wherein a first set of nanowires or a first set of 2D material strips in the patterned conductors is arranged as a first patterned conductor in a first direction over an area where channels of the first transistor and the second transistor are disposed, and a second set of nanowires or a second set of 2D material strips in the patterned conductors is arranged as a second patterned conductor in a second direction orthogonal to the first direction and over the first set of nanowires.
2 more elements
A circuit, comprising:
- a first transistor;
- a second transistor;
- and
- an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or one or more 2D material strips arranged in parallel,
- wherein said one or more nanowires or said one or more 2D material strips of the interconnect includes/include a set of nanowires or a set of 2D material strips disposed in a plurality of stacks.
2 more elements
A circuit, comprising:
- a substrate;
- a first interconnect, comprising one or more nanowires or 2D material strips connected in parallel and disposed vertically relative to a surface of the substrate;
- a second interconnect, comprising one or more nanowires or 2D material strips connected in parallel and disposed horizontally relative to the surface of the substrate, nanowires or 2D material strips in the second interconnect connected to nanowires or 2D material strips in the first interconnect;
- and
- a transistor having a channel comprising a set of nanowires or a set of 2D material strips arranged in parallel and disposed vertically relative to a surface of the substrate, having a source/drain terminal connected to the second interconnect.
2 more elements
A circuit, comprising:
- a substrate;
- a vertical set of one or more nanowires or a vertical set of one or more 2D material strips connected in parallel and disposed vertically relative to a surface of the substrate, and having a channel region;
- a first horizontal set of one or more nanowires or a first horizontal set of one or more 2D material strips connected in parallel to the vertical set of one or more nanowires or the vertical set of one or more 2D material strips and disposed horizontally relative to a surface of the substrate below the channel region;
- and
- a second horizontal conductor connected to the vertical set of one or more nanowires or the vertical set of one or more 2D material strips and disposed horizontally relative to a surface of the substrate above the channel region.
2 more elements
A computer system adapted to process a computer implemented representation of a circuit design, the computer system comprising:
- a processor and a memory coupled to the processor, the memory storing instructions that, when executed by the processor, cause the processor to select cells from a cell library;
- the cell library including entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language;
- and
- at least one entry in the cell library comprising a specification of physical structures and timing parameters of a circuit including:
- a substrate;
- a first interconnect, comprising one or more nanowires or 2D material strips connected in parallel and disposed vertically relative to a surface of the substrate;
- and
- a second interconnect, comprising one or more nanowires or 2D material strips connected in parallel and disposed horizontally relative to the surface of the substrate, nanowires or 2D material strips in the second interconnect connected to nanowires or 2D material strips in the first interconnect.
5 more elements
A computer system adapted to process a computer implemented representation of a circuit design, the computer system comprising:
- a processor and a memory coupled to the processor, the memory storing instructions that, when executed by the processor, cause the processor to select cells from a cell library;
- the cell library including entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language;
- and
- at least one entry in the cell library comprising a specification of physical structures and timing parameters of a circuit including:
- a substrate;
- a vertical set of one or more nanowires or a vertical set of one or more 2D material strips connected in parallel and disposed vertically relative to a surface of the substrate, and having a channel region;
- a first horizontal set of one or more nanowires or a first horizontal set of one or more 2D material strips connected in parallel to the vertical set of one or more nanowires or the vertical set of one or more 2D material strips and disposed horizontally relative to a surface of the substrate below the channel region;
- and
- a second horizontal conductor connected to the vertical set of one or more nanowires or the vertical set of one or more 2D material strips and disposed horizontally relative to a surface of the substrate above the channel region.
6 more elements
A computer program product, comprising:
- a memory device having stored thereon a machine readable specification of a cell, the specification of the cell including computer readable parameters specifying structural features of a physical implementation of a circuit, the specification being executable by a computer running a placement process to control physical placement of the circuit with other circuits or components, the circuit comprising:
- a substrate;
- a first interconnect, comprising one or more nanowires or 2D material strips connected in parallel and disposed vertically relative to a surface of the substrate;
- a second interconnect, comprising one or more nanowires or 2D material strips connected in parallel and disposed horizontally relative to the surface of the substrate, nanowires or 2D material strips in the second interconnect connected to nanowires or 2D material strips in the first interconnect;
- and
- a transistor having a channel comprising a set of nanowires or a set of 2D material strips arranged in parallel and disposed vertically relative to a surface of the substrate, having a source/drain terminal connected to the second interconnect.
3 more elements
A computer program product, comprising:
- a memory device having stored thereon a machine readable specification of a cell, the specification of the cell including computer readable parameters specifying structural features of a physical implementation of a circuit, the specification being executable by a computer running a placement process to control physical placement of the circuit with other circuits or components, the circuit comprising:
- a substrate;
- a vertical set of one or more nanowires or a vertical set of one or more 2D material strips connected in parallel and disposed vertically relative to a surface of the substrate, and having a channel region;
- a first horizontal set of one or more nanowires or a first horizontal set of one or more 2D material strips connected in parallel to the vertical set of one or more nanowires or the vertical set of one or more 2D material strips and disposed horizontally relative to a surface of the substrate below the channel region;
- and
- a second horizontal conductor connected to the vertical set of one or more nanowires or the vertical set of one or more 2D material strips and disposed horizontally relative to a surface of the substrate above the channel region.
3 more elements
Dependencies are inferred from the claim text.