Linear Stage for reflective electron beam lithography

A linear stacked stage, comprising:

• a first upper fast stage configured to translate a first plurality of wafers in a first direction along a first axis at a first selected speed, the first upper fast stage configured to secure the first plurality of wafers;
• a second upper fast stage configured to translate a second plurality of wafers in a second direction along the first axis at a second selected speed, the second upper fast stage configured to secure the second plurality of wafers;
• and
• a carrier stage configured to translate the first upper fast stage and the second upper fast stage along a second axis substantially orthogonal to the first axis at a third selected speed, the first upper fast stage and the second upper fast stage disposed on the surface of the carrier stage, wherein the first upper fast stage, the second upper fast stage and the carrier stage are configured to scan one or more wafers of at least one of the first plurality of wafers or the second plurality of wafers under a plurality of electron columns,
• wherein the third selected speed of the carrier stage is slower than the first selected speed of the first upper fast stage and the second selected speed of the second upper fast stage.

A linear stacked stage, comprising:

• a first plurality of upper fast stages;
• a second plurality of upper fast stages, each upper fast stage of the first plurality of upper fast stages corresponding to an upper fast stage in the second plurality of upper fast stages, each upper fast stage of the first plurality configured to translate a wafer in a first direction along a first axis at a first selected speed, each corresponding upper fast stage of the second plurality configured to translate an additional wafer in a second direction along the first axis at a second selected speed, the second direction opposite to the first direction, wherein the translation of each upper fast stage of the first plurality and the translation of each corresponding upper fast stage of the second plurality are configured to substantially eliminate inertial reaction forces generated by motion of the first plurality of upper fast stages and the second plurality of upper fast stages;
• and
• a carrier stage configured to translate the first plurality of upper fast stages and the second plurality of upper fast stages along a second axis substantially orthogonal to the first axis at a third selected speed, the first plurality of upper fast stages and the second plurality of upper fast stages disposed on the surface of the carrier stage, wherein the first plurality of upper fast stages, the second plurality of upper fast stages and the carrier stage are configured to scan at least one wafer under a plurality of electron columns,
• wherein the third selected speed of the carrier stage is slower than the first selected speed of the first upper fast stage and the second selected speed of the second upper fast stage.

A linear stacked stage, comprising:

• a first upper fast stage configured to translate a first plurality of wafers along at least one of a first axis and a second axis at a first selected speed, the first upper fast stage configured to secure the first plurality of wafers;
• a second upper fast stage configured to translate a second plurality of wafers along at least one of the first axis and the second axis at a second selected speed, the second upper fast stage configured to secure the second plurality of wafers;
• and
• a fixed carrier stage configured to support the first upper fast stage and the second upper fast stage, wherein the first upper fast stage, the second upper fast stage and the carrier stage are configured to scan one or more wafers of at least one of the first plurality of wafers or the second plurality of wafers under a plurality of electron columns.

A lithography probe system, comprising:

• at least one plurality of electron optical columns;
• a stacked scanning stage comprising:
• a first upper fast stage configured to translate a first wafer along at least one of a first axis and a second axis at a first selected speed;
• a second upper fast stage configured to translate a second wafer along at least one of a first axis and a second axis at a second selected speed;
• a carrier stage, the first upper fast stage and the second upper fast stage disposed on an upper surface of the carrier stage, the carrier stage configured to translate at least one of the first upper fast stage and the second upper fast stage along at least one of the first axis and the second axis at a third selected speed, the stacked scanning stage configured to scan at least one of the first wafer or the second wafer under the at least one plurality of electron optical columns,
• wherein the third selected speed of the carrier stage is slower than the first selected speed of the first upper fast stage and the second selected speed of the second upper fast stage.

A lithography production system, comprising:

• two or more pluralities of electron optical columns;
• a stacked scanning stage configured to translate one or more wafers under at least one of the two or more pluralities of electron optical columns, the stack scanning stage comprising:
• a first upper fast stage configured to translate a first wafer along at least one of a first axis and a second axis at a first selected speed;
• a second upper fast stage configured to translate a second wafer along at least one of a first axis and a second axis at a second selected speed;
• and
• a carrier stage, the first upper fast stage and the second upper fast stage disposed on an upper surface of the carrier stage, the carrier stage configured to translate at least one of the first upper fast stage and the second upper fast stage along at least one of the first axis and the second axis at a third selected speed,
• wherein the third selected speed of the carrier stage is slower than the first selected speed of the first upper fast stage and the second selected speed of the second upper fast stage.