Apparatus and method for performing absolute difference operation

An apparatus comprising:

• processing means for performing an absolute difference operation to generate an absolute difference value in response to a first operand and a second operand, wherein the first operand, the second operand and the absolute difference value each comprise at least one data element having a current data element size selected from a plurality of data element sizes, and each data element of the absolute difference value represents an absolute difference between corresponding data elements of the first and second operands;
• the processing means comprising:
• adding means for performing at least one addition using corresponding portions of the first operand and the second operand to generate at least one intermediate value, and to generate status information in dependence on said at least one addition, wherein each portion comprises a whole or part of a data element having said current data element size;
• inverting means for selectively inverting selected bits of the at least one intermediate value to convert the at least one intermediate value into at least one corresponding portion of the absolute difference value;
• and
• control means for generating, in response to the current data element size and said status information control information identifying said selected bits of the at least one intermediate value.

A method of performing an absolute difference operation to generate an absolute difference value in response to a first operand and a second operand, wherein the first operand, the second operand and the absolute difference value each comprise at least one data element having a current data element size selected from a plurality of data element sizes, and each data element of the absolute difference value represents an absolute difference between corresponding data elements of the first and second operands;

• the method comprising:
• processing circuitry performing at least one addition using corresponding portions of the first operand and the second operand to generate at least one intermediate value, and generating status information in dependence on said at least one addition, wherein each portion comprises a whole or part of a data element having said current data element size;
• in response to the current data element size and said status information, control circuitry generating control information identifying selected bits of the at least one intermediate value;
• and
• an inverter stage inverting the selected bits of the at least one intermediate value indicated by the control information to convert the at least one intermediate value into at least one corresponding portion of the absolute difference value.