Time base including an oscillator, a frequency divider circuit and clocking pulse inhibition circuit

A method for adjusting the frequency of at least one clock signal produced by a time base including an oscillator generating a periodic signal having a natural frequency higher than a reference value, a frequency divider circuit formed by a division chain defining several division stages, said divider circuit receiving, at input, said periodic signal and delivering, at output, said at least one clock signal with a divided frequency, a divided frequency adjustment circuit functioning by inhibiting, in each inhibition period of a plurality of successive inhibition periods, an integer number of clocking pulses at the input of a given stage of said division chain, said method for adjusting the frequency of at least one clock signal comprising:

• A) providing, in each inhibition period, a first real number corresponding to said inhibition period multiplied by the difference between a determined clocking frequency, produced by the division stage preceding said given stage or by the oscillator when said given stage is the first stage of the division chain, and a reference frequency for clocking said given stage;
• B) calculating, in each inhibition period, a second real number which, in a first inhibition period, is equal to said first real number and then in each subsequent inhibition period, is equal to the addition of said first real number and the fractional part of the second real number obtained for the preceding inhibition period;
• and
• C) inhibiting, in each inhibition period, the integer part of said second real number calculated in said inhibition period.