Flip chip packaging
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Chih Liu, Chien-Kuo Chang, Chi-Yang Yu, Jing Ruei Lu, Chih-Hao Lin
Life of this patent
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Abstract
An integrated circuit (IC) package includes a first substrate; a second substrate disposed over the first substrate; a plurality of connectors disposed between the first and second substrates such to electrically couple the first and second substrate; a constraint layer disposed over the first and second substrates such that a cavity is formed between the constraint layer and the first substrate; and a molding material disposed within the cavity and extending through the constraint layer. The constraint layer has a top surface and an opposing bottom surface and the molding material extends from the top surface to the bottom surface of the constraint layer.
Claims20
A method comprising:
- providing a package substrate;
- coupling a device substrate to the package substrate via a solder connector such that the device substrate and the package substrate are electrically coupled together;
- forming a constraint layer that includes an opening over the package substrate and the device substrate, wherein a cavity is defined between the constraint layer and the package substrate;
- and
- filling, through the opening of the constraint layer, the cavity with a molding material to surround the solder connector such that the molding material physically contacts the solder connector.
A method comprising:
- coupling a device substrate to a package substrate via a solder connector such that the device substrate and the package substrate are electrically coupled together;
- forming a metallic layer with an opening over the device and package substrates, wherein a cavity is defined between the metallic layer and the package substrate;
- and
- forming a molding material in the cavity through the opening to surround the solder connector such that the molding material physically contacts the solder connector.
A method comprising:
- coupling a device substrate to a package substrate via a solder connector such that the device substrate and the package substrate are electrically coupled together;
- forming an interface layer on the device substrate;
- forming a constraint layer over the interface layer, device substrate, and package substrate, wherein a cavity is defined between the constraint layer and the package substrate;
- forming a molding material in the cavity to surround the solder connector such that the molding material physically contacts the solder connector;
- and
- curing the molding material in the cavity.
Dependencies are inferred from the claim text.