Stacked transistors with different channel widths

A method for forming a semiconductor device, the method comprising:

• forming a stack of nanosheets on a substrate, the stack of nanosheets comprising a first layer of a first nanosheet material arranged on the substrate and a second layer of a second nanosheet material arranged on the first layer, a third layer of the first nanosheet material arranged on the second layer, a fourth layer of the second nanosheet material arranged on the third layer, a fifth layer of the first nanosheet material arranged on the fourth layer and a sixth layer of the second nanosheet material arranged on the fifth layer
• removing portions of the stack of nanosheets to form a nanosheet fin on the substrate;
• forming a first sacrificial gate on a first channel region of the nanosheet fin, a second sacrificial gate on a second channel region of the nanosheet fin, and a third sacrificial gate on a third channel region of the nanosheet fin;
• forming a first sacrificial spacer along sidewalls of the first sacrificial gate, the second sacrificial gate, and the third sacrificial gate;
• removing exposed portions of the nanosheet fin;
• removing portions of the first nanosheet material to form cavities in the nanosheet fin;
• filling the cavities with a second sacrificial spacer;
• removing the first sacrificial spacer from along the sidewalls of the first sacrificial gate, the second sacrificial gate, and the third sacrificial gate;
• depositing an insulator material over the substrate and the sidewalls of the first sacrificial gate, the second sacrificial gate, and the third sacrificial gate;
• removing portions of the insulator material to form a spacer adjacent to sidewalls of the first sacrificial gate, the second sacrificial gate, and the third sacrificial gate, and to expose the sixth layer and the fifth layer;
• removing additional portions of the insulator material to expose portions of the fourth layer and the third layer, wherein the exposed portions of the fourth layer, and the third layer are arranged under the second sacrificial gate and the third sacrificial gate;
• removing additional portions of the insulator material to expose portions of the second layer and the first layer, wherein the exposed portions of the second layer and the first layer are arranged under the third sacrificial gate;
• forming source/drain regions adjacent to the first sacrificial gate, the second sacrificial gate, and the third sacrificial gate;
• and
• forming a gate stack over the first channel region, the second channel region, and the third channel region.