Near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine
AssigneeIntel Corporation
InventorsKarthikeyan Vaithianathan, Arvind Sudarsanam
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Abstract
Embodiments of a near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine are generally described herein. Other embodiments may be described and claimed. In some embodiments, a configurable two-dimensional adder tree architecture for computing a sum of absolute differences (SAD) for various block sizes up to 16 by 16 comprises a first stage of one-dimensional adder trees and a second stage of one-dimensional adder trees, wherein each one-dimensional adder tree comprises an input routing network, a plurality of adder units, and an output routing network.
Claims20
A integrated circuit having a configurable two-dimensional adder tree architecture for computing a sum of array elements of arbitrary block sizes up to 16 by 16, the integrated circuit comprising:
- a first stage of the configurable two-dimensional adder tree architecture containing a plurality of one-dimensional adder trees;
- and
- a second stage of the configurable two-dimensional adder tree architecture containing a plurality of one-dimensional adder trees, wherein each and every one-dimensional adder tree of both the first and second stages of one-dimensional adder trees comprises:
- an input routing network;
- 15 adder units;
- an output routing network;
- a first plurality of routing wires connecting the 15 adder units to the input routing network;
- and
- a second plurality of routing wires connecting the 15 adder units to the output routing network.
An integrated circuit device comprising:
- a configurable two-dimensional adder tree architecture for computing a sum of array elements of arbitrary block sizes up to 16 by 16 comprising:
- a first stage containing a plurality of one-dimensional adder trees;
- and
- a second stage containing a plurality of one-dimensional adder trees, wherein each and every one-dimensional adder tree of both the first and second stages of one-dimensional adder trees comprises:
- an input routing network comprising a first plurality of multiplexers implemented in hardware;
- a plurality of adder units;
- and
- an output routing network, wherein the output routing network comprises 39 2-to-1 multiplexers implemented in hardware.
A system comprising:
- a network controller;
- a system memory;
- and
- a processor, the processor comprising:
- a configurable two-dimensional adder tree architecture for computing a sum of array elements of arbitrary block sizes up to 16 by 16 comprising:
- a first stage containing a plurality of one-dimensional adder trees;
- and
- a second stage containing a plurality of one-dimensional adder trees, wherein each and every one-dimensional adder tree of both the first and second stages of one-dimensional adder trees comprises:
- an input routing network, wherein the input routing network comprises 20 2-to-1 multiplexers;
- a plurality of adder units connected to the 20 2-to-1 multiplexers by a first plurality of routing wires;
- and
- an output routing network.
Dependencies are inferred from the claim text.