Connection structure for vertical gate all around (VGAA) devices on semiconductor on insulator (SOI) substrate

A memory cell structure, comprising:

• a plurality of memory cells, each memory cell comprising two cross-coupled inverters having a data storage node and a complementary data storage node, each inverter comprising a P-type VGAA nanowire pull-up (PU) device, an N-type VGAA nanowire pull-down (PD) device, and first and second pass-gate (PG) devices, each pass-gate device being an N-type VGAA nanowire device, wherein the P-type and N-type VGAA nanowire devices are formed on a semiconductor-on-insulator (SOT) substrate, each of the VGAA nanowire devices comprising (i) a gate layer including a high-K gate dielectric and a metal layer, (ii) a nanowire having a first height, a first width, and a first depth, (iii) a bottom plate, (iv) a top plate having a second width that is greater than the first width and a second depth that is greater than the first depth, wherein one of the bottom and top plates serves as a drain node and the other of the bottom and top plates serves as a source node for the VGAA nanowire device, and (v) a contact formed over the top plate;
• each cell comprising (i) a first common bottom plate of a first pull-down (PD-1) VGAA device, a first pull-up (PU-1) VGAA device, and a first pass-gate (PG-1) VGAA device, and (ii) a second common bottom plate of a second pull-down (PD-2) VGAA device, a second pull-up (PU-2) VGAA device, and a second pass-gate (PG-2) VGAA device;
• each cell comprising four gate layers, a first gate layer comprising a gate node of the first inverter, a second gate layer comprising a gate node of the second inverter, a third gate layer comprising a gate node of the first pass-gate device and a fourth gate layer comprising a gate node of the second pass-gate device.

A vertical gate all around (VGAA) nanowire device circuit routing structure, comprising:

• a plurality of VGAA nanowire devices including a NMOS VGAA nanowire device and a PMOS VGAA nanowire device, the VGAA nanowire devices having been formed on a semiconductor-on-insulator (SOI) substrate, each VGAA nanowire device comprising a bottom plate and a top plate wherein one of the bottom and top plates serves as a drain node and the other of the bottom and top plates serves as a source node, each VGAA nanowire device further comprising a gate layer, the gate layer comprising a high-K gate dielectric and a metal layer, the gate layer fully surrounding a vertical channel in the VGAA nanowire device and serving as a gate node;
• and
• a CMOS circuit formed by the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the CMOS circuit further comprising a common top plate that includes a silicon-based block shared by the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the silicon-based block electrically coupling a drain node of the NMOS VGAA nanowire device to a drain node of the PMOS VGAA nanowire device, the CMOS circuit comprising a gate layer that serves as a common gate for the NMOS VGAA nanowire device and the PMOS VGAA nanowire device, the CMOS circuit comprising a first bottom plate that serves as the source node for the NMOS VGAA nanowire device and a second bottom plate that serves as the source node for the PMOS VGAA nanowire device, wherein the first bottom plate is electrically connected to a Vss conductor and the second bottom plate is electrically connected to a Vdd conductor.