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US 9,653,468 B2Granted
Memory cells having a folded digit line architecture
AssigneeMicron Technology, Inc.
InventorShigeki Tomishima
Life of this patent
Estimating the term…
Abstract
Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row.
Claims21
An apparatus comprising:
- first and second semiconductor active regions;
- a first trench formed in the first semiconductor active region to define first and second legs, wherein the first and second legs sandwich the first trench therebetween;
- a second trench formed in the second semiconductor active region to define third and fourth legs, wherein the third and fourth legs sandwich the second trench therebetween;
- first conductive line in electrical contact with the first leg, wherein the first conductive line is elongated to pass through over the second trench with an electrical isolation from each of the third and fourth legs;
- and
- a second conductive line in electrical contact with the third leg, wherein the second conductive line is elongated to pass through over the first trench with an electrical isolation from each of the first and second legs.
3 more elements
An apparatus comprising:
- a first memory cell access transistor including first and second source/drain regions and a first channel region therebetween;
- a second memory cell access transistor including third and fourth source/drain regions and a second channel region therebetween;
- a first word line extending to control the first channel region of the first memory cell access transistor;
- a second word line extending to control the second channel region of the second memory cell access transistor;
- a first digit line in electrical contact with the first source/drain region of the first memory cell access transistor, the first digit line extending over the second channel region and between the third and fourth source/drain regions of the second memory cell access transistor;
- and
- a second digit line in electrical contact with the third source/drain region of the second memory cell, the second digit line extending over the first channel region and between the first and second source/drain regions of the first memory cell access transistor.
4 more elements
An apparatus comprising:
- a plurality of finFETs arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of finFETs comprises a first leg, a second leg, and a shallow trench formed therebetween;
- a plurality of word lines, wherein each of the plurality of word lines is elongated along ones of the plurality of finFETs in an associated one of the plurality of rows;
- and
- a plurality of first digit lines, wherein each of the plurality of first digit lines is elongated so as to have an electrical contact with the first leg of each of even-numbered ones of the finFETs in an associated one of the plurality of columns and pass through over the shallow trench of each of odd-numbered ones of the plurality of finFETs in the associated one of the plurality of columns with an electrical isolation from each of the first and second legs of each of the odd-numbered ones of the plurality of finFETs in the associated one of the plurality of columns.
1 more element
Dependencies are inferred from the claim text.