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US 9,645,603 B1Granted
System clock distribution in a distributed computing environment
AssigneeAdvanced Processor Architectures, LLC
InventorsLouis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
Life of this patent
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Abstract
A system clock signal is distributed to computing devices within a distributed computing system. The distributed computing devices, which may be dual-die chip carriers, include input and output ports on which system clock signals are propagated. The input and/or output ports of various distributed computing devices may be configured and reconfigured according to system preferences or requirements.
Claims22
A distributed computing system configured to distribute clock signals to interconnected integrated circuit dies, the system comprising:
- a system clock generator configured to generate a system clock signal;
- and
- a plurality of distributed interconnected integrated circuit dies, wherein at least some of the plurality of interconnected integrated circuit dies comprise:
- a unidirectional receive serial connection to each of at least three neighboring dies;
- a unidirectional transmit serial connection to each of the at least three neighboring dies;
- a plurality of independently-configurable inputs capable of receiving a clock signal, wherein a clock input is selected from the plurality of independently-configurable inputs to receive the clock signal based on a selection of a clock distribution scheme, and wherein data is superimposed on the clock signal at least a portion of the time that the interconnected integrated circuit die receives the clock signal;
- and
- a plurality of independently-configurable outputs capable of transmitting a clock signal, wherein a clock output is selected from the plurality of independently-configurable outputs to output the clock signal based on the selection of the clock distribution scheme, and wherein data is superimposed on the clock signal at least a portion of the time that the interconnected integrated circuit die outputs the clock signal;
- wherein the system clock signal is provided by the system clock generator and distributed to each of the plurality of interconnected integrated circuit dies based at least in part on data communication requirements of the distributed computing system.
6 more elements
A method of distributing a single-frequency clock signal within a distributed computing system having interconnected integrated circuit chips, the method comprising:
- generating a system clock signal of a single frequency;
- providing the system clock signal to a first integrated circuit die of a plurality of interconnected integrated circuit dies via a first input of the first integrated circuit die, wherein the first integrated circuit die includes a plurality of inputs capable of receiving the system clock signal, and wherein the first input is selected from the plurality of inputs based at least in part on a designated system clock distribution network;
- and
- providing a copy of the system clock signal from the first integrated circuit die to a second integrated circuit die of the plurality of integrated circuit dies over a configurable input port of the second integrated circuit die, wherein the second integrated circuit die includes a plurality of inputs capable of receiving the copy of the system clock signal, and wherein the configurable input port is selected from the plurality of inputs based at least in part on the designated clock distribution scheme;
- wherein each of the plurality of interconnected integrated circuit dies receives a master clock signal of the single frequency according to the system clock distribution network.
2 more elements
A computing system configured to distribute clock signals to many interconnected integrated circuit dies, the system comprising:
- a system clock generator configured to generate a system clock signal and provide the system clock signal over a first output line;
- and
- a plurality of interconnected integrated circuit dies comprising:
- a first integrated circuit die having a plurality of independently-configurable first input lines and independently-configurable first output lines, wherein the plurality of first input lines include a master clock input line in electrical communication with the first output line of the system clock generator for receiving the system clock signal, wherein the plurality of first output lines include a primary clock output line configured to output a copy of the system clock signal, wherein the master clock input line is selected from the plurality of first input lines based on a selection of a clock distribution scheme;
- and
- a second integrated circuit die having a plurality of independently-configurable second input lines and independently-configurable second output lines, wherein the second integrated circuit die is configured to receive the copy of the system clock signal on one of the second input lines, wherein the one of the second input lines is selected based on the selection of the clock distribution scheme, wherein data is superimposed on the copy of the system clock signal at least a portion of the time that the second integrated circuit die receives the copy of the system clock signal;
- wherein the primary clock output line remains active during system operation.
4 more elements
Dependencies are inferred from the claim text.