# US 9,645,191 B2 · Testing and setting performance parameters in a semiconductor device and method therefor

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- Number: US 9,645,191 B2
- Document ID: US9645191B2
- Status: Granted
- Kind: B2
- Application number: 14/484,593
- Filed: 2014-09-12
- Published: 2016-02-25
- Granted: 2017-05-09
- Earliest claimed: 2014-08-20
- Applicants: Darryl G. Walker
- Inventors: Darryl G. Walker
- Web page: https://patentgrep.com/patent/US9645191B2

## CPC

- G01R 31/50: Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections (testing of sparking plugs H01T13/58)
- G01R 31/2628: {for measuring thermal properties thereof}
- G01R 31/2875: {related to heating}
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 11/40626: {Temperature related aspects of refresh operations}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/50: Marginal testing, e.g. race, voltage or current testing
- G11C 29/50016: {of retention}
- G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]}
- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 29/006: {at wafer scale level, i.e. wafer scale integration [WSI]}
- G11C 2029/5002: {Characteristic}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.

## Claims

### Claim 1

A method of setting performance parameters based on temperature in a plurality of semiconductor devices on a contiguous wafer, each semiconductor device including a temperature sensing circuit wherein the wafer includes a plurality of regions, each region including a plurality of semiconductor devices, comprising the steps of:
testing the operation of circuitry different than the temperature sensing circuit in one of the plurality of semiconductor devices in each region at a plurality of temperatures to determine a plurality of regional performance parameters corresponding to each one of the plurality of regions, each one of the plurality of temperatures in a corresponding one of a plurality of temperature ranges; wherein
each one of the plurality of semiconductor devices includes a performance parameter table and the method further includes the step of writing corresponding regional performance parameters to the performance parameter table for each one of the plurality of semiconductor devices for each corresponding region.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
each one of the plurality of temperatures has a temperature value that is within a predetermined one of the plurality of temperature ranges set by the temperature sensing circuit.

### Claim 3 (depends on 2)

The method of claim 2, wherein:
the temperature value of each one of the plurality temperatures is essentially a midpoint of the predetermined one of the plurality of temperature ranges set by the temperature sensing circuit.

### Claim 4 (depends on 1)

The method of claim 1, wherein:
each region includes a centrally located semiconductor device and a plurality of adjacent semiconductor devices and only the centrally located semiconductor device is tested in the step of testing the operation of one of the plurality of semiconductor devices in each region.

### Claim 5 (depends on 1)

The method of claim 1, further including the step of:
dicing the wafer to separate the plurality of semiconductor devices.

### Claim 6 (depends on 5)

The method of claim 5, wherein:
the step of testing the operation and the step of writing corresponding regional performance parameters are performed before the step of dicing the wafer.

### Claim 7 (depends on 5)

The method of claim 5, wherein:
the step of testing the operation is performed before the step of dicing the wafer and the step of writing corresponding regional performance parameters is performed after the step of dicing the wafer.

### Claim 8 (depends on 5)

The method of claim 5, further including the step of:
packaging each one of the semiconductor devices.

### Claim 9 (depends on 8)

The method of claim 8, further including the step of:
the step of testing the operation is performed before the step of dicing the wafer and the step of writing corresponding regional performance parameters is performed after the step of packaging each one of the semiconductor devices.

### Claim 10

A method of setting performance parameters based on temperature in a plurality of semiconductor devices on a contiguous wafer, each semiconductor device including a temperature sensing circuit wherein the wafer includes a plurality of regions, each region including a plurality of semiconductor devices, comprising the steps of:
testing the operation of circuitry different than the temperature sensing circuit in one of the plurality of semiconductor devices in each region at a plurality of temperatures to determine a plurality of regional performance parameters corresponding to each one of the plurality of regions, each one of the plurality of temperatures in a corresponding one of a plurality of temperature ranges; wherein
the step of testing includes determining the plurality of regional performance parameters corresponding to each one of the plurality of regions based on a desired operating specification for the plurality of semiconductor devices.

### Claim 11 (depends on 10)

The method of claim 10, wherein:
the operating specification is a timing specification.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
the timing specification is an access time.

### Claim 13 (depends on 12)

The method of claim 12, wherein:
each of the plurality of semiconductor devices is a memory device.

### Claim 14 (depends on 11)

The method of claim 11, wherein.
the timing specification is a clock period.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
each of the plurality of semiconductor devices is a processor.

### Claim 16 (depends on 10)

The method of claim 10, wherein:
the operating specification is a current specification.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
the current specification is a standby current.

### Claim 18 (depends on 16)

The method of claim 16, wherein:
the current specification is an active current.

### Claim 19 (depends on 16)

The method of claim 16, wherein:
the current specification is an average current.