Input signal mismatch detection circuit

An event detection system, comprising:

• first and second sensors for detecting acceleration of a body and generating first and second output signals;
• a first analog-to-digital converter (ADC) connected to the first sensor for receiving the first output signal and generating a first digital output signal;
• a second ADC connected to the second sensor for receiving the second output signal and generating a second digital output signal;
• a time-division multiplexing (TDM) circuit connected to the first and second ADCs for receiving and time-division multiplexing the first and second digital output signals, and outputting a TDM signal;
• a first processor connected to the TDM circuit for receiving the TDM signal and generating a first processed output signal;
• a time-division de-multiplexing (TDDM) circuit connected to the first processor for receiving and time-division de-multiplexing the first processed output signal, and outputting first and second TDDM signals;
• a second processor connected to the first ADC for receiving the first digital output signal and generating a second processed output signal;
• a first gating circuit, connected to the TDDM circuit and the second processor, for receiving and comparing the first TDDM signal and the second processed output signal, and generating a first gating signal;
• a third processor connected to the second ADC for receiving the second digital output signal and generating a third processed output signal,
• wherein the first processor comprises:
• a first sinc filter connected to the TDM circuit for receiving the TDM signal and generating a first sinc output signal;
• a first trimmer connected to the first sinc filter for receiving the first sinc output signal and generating a first trim output signal;
• a first infinite impulse response (IIR) filter connected to the first trimmer for receiving the first trim output signal and generating a first filter output signal;
• and
• a first high pass filter (HPF) connected to the first IIR filter for receiving the first filter output signal and generating the first processed output signal,
• wherein the second processor comprises:
• a second sinc filter connected to the first ADC for receiving the first digital output signal and generating a second sinc output signal;
• a second IIR filter connected to the second sinc filter for receiving the second sinc output signal and generating a second filter output signal;
• and
• a second HPF connected to the second IIR filter for receiving the second filter output signal and generating the second processed output signal,
• wherein the third processor comprises:
• a third sinc filter connected to the second ADC for receiving the second digital output signal and generating a third sinc output signal;
• a third IIR filter connected to the third sinc filter for receiving the third sinc output signal and generating a third filter output signal;
• and
• a third HPF connected to the third IIR filter for receiving the third filter output signal and generating the third processed output signal,
• wherein bandwidths of the second and third IIR filters are greater than a bandwidth of the first IIR filter, and bandwidths of the second and third HPFs are greater than a bandwidth of the first HPF,
• a second gating circuit, connected to the TDDM circuit and the third HPF, for receiving and comparing the second TDDM signal and the third processed output signal, and generating a second gating signal;
• and
• an engine control unit (ECU) connected to the first gating circuit for receiving the first gating signal, and to the second gating circuit for receiving the second gating signal and executing pre-stored event detection algorithms using the first gating signal and the second gating signal, wherein the pre-stored event detection algorithms determine whether a trigger signal is generated.