Circuits and methods providing clock frequency adjustment in response to supply voltage changes

A method comprising:

• receiving a plurality of input voltages at a voltage comparator and at a plurality of respective voltage measurement circuits;
• generating a control signal by the voltage comparator in response to determining that one or more of the input voltages droops by a threshold amount;
• in response to the control signal, causing an oscillator circuit to enter an open-loop operating mode and to divide an output frequency of the oscillator circuit;
• generating frequency adjustment signals by the voltage measurement circuits in response to the plurality of input voltages;
• and
• adjusting an oscillator frequency of the oscillator circuit in response to the frequency adjustment signals, wherein adjusting the oscillator frequency of the oscillator circuit in response to the frequency adjustment signals comprises:
• stopping dividing the output frequency of the oscillator circuit;
• and
• iteratively stepping up the oscillator frequency of the oscillator circuit to return an output clock signal to a frequency range associated with non-droop levels of the input voltage.

A method comprising:

• receiving a plurality of power supply voltages at a plurality of respective voltage sensors, and receiving the plurality of power supply voltages at a comparator as a clock circuit operates at a first output frequency;
• in a first control system, detecting a droop in at least one of the power supply voltages using the comparator, and in response to detecting the droop, causing a phase locked loop (PLL) of the clock circuit to enter an open-loop mode, and dividing the first output frequency so that the clock circuit operates at a second output frequency;
• in a second control system, detecting the droop in at least one of the power supply voltages using at least one of the voltage sensors, and in response to detecting the droop, causing an oscillator of the PLL to lower its oscillating frequency;
• and
• further comprising in the first control system:
• stopping dividing the first output frequency of the clock circuit and iteratively stepping up the oscillating frequency of the oscillator in pre-programmed steps.

A method comprising:

• receiving a plurality of power supply voltages at a plurality of respective voltage sensors, and receiving the plurality of power supply voltages at a comparator as a clock circuit operates at a first output frequency;
• in a first control system, detecting a droop in at least one of the power supply voltages using the comparator, and in response to detecting the droop, causing a phase locked loop (PLL) of the clock circuit to enter an open-loop mode, and dividing the first output frequency so that the clock circuit operates at a second output frequency;
• and
• in a second control system, detecting the droop in at least one of the power supply voltages using at least one of the voltage sensors, and in response to detecting the droop, causing an oscillator of the PLL to lower its oscillating frequency, wherein the second control system causing the oscillator of the PLL to lower its oscillating frequency results in the clock circuit operating at a third output frequency lower than the second output frequency;
• and
• further wherein the first control system stops a dividing operation, thereby causing the clock circuit to operate at a fourth output frequency, which is a multiple of the third output frequency but lower than the first output frequency.

A system comprising:

• a plurality of voltage inputs;
• means for generating a control signal in response to determining that one or more of the voltage inputs droops by a threshold amount;
• means for causing an oscillator circuit to enter an open-loop operating mode and to divide an output frequency of the oscillator circuit, including means to select a divided output frequency in response to the control signal;
• means for generating frequency adjustment signals in response to the plurality of input voltages;
• and
• means for adjusting an oscillator frequency of the oscillator circuit in response to the frequency adjustment signals.