Memory module, memory system including the same and operation method thereof
AssigneeSK hynix Inc.
InventorsJing-Zhe Xu, Yong-Ju Kim, Jung-Hyun Kwon, Sung-Eun Lee, Jae-Sun Lee
Life of this patent
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Abstract
A memory system may include a memory module comprising a plurality of memory chips mounted therein each memory chip comprising a plurality of banks, the memory chips being simultaneously accessible based on the same command and address; and a memory controller suitable for mapping the banks of the memory chips to each other while rearranging an order of the banks of each of the memory chips based on repair information of the memory chips.
Claims20
A memory system comprising:
- a memory module comprising a plurality of memory chips mounted therein each memory chip comprising a plurality of banks, the memory chips being simultaneously accessible based on the same command and address;
- and
- a memory controller suitable for mapping the banks of the memory chips to each other while rearranging an order of the banks of each of the memory chips based on repair information of the memory chips.
A memory module comprising:
- a plurality of memory chips suitable for being simultaneously accessed based on the same command and address and each comprising a plurality of banks mapped to respective banks of the other memory chips,
- wherein each of the memory chips comprises:
- a memory array region having the plurality of banks arranged therein, the plurality of banks each including normal cells and redundancy cells for replacing repair target cells among the normal cells;
- a repair storage unit suitable for storing repair addresses of the repair target cells, and outputting the repair addresses as repair information;
- a repair control unit suitable for comparing the repair information and a row address, and generating a repair control signal for selectively enabling redundant paths between the repair target cells and the redundancy cells;
- a bank control unit suitable for generating a plurality of bank select signals by decoding a bank address, generating a plurality of bank enable signals based on the bank select signals, and rearranging the order of the bank select signals in response to a mapping signal;
- a row circuit suitable for enabling a word line corresponding to the row address based on the bank select signals and the repair control signal;
- and
- a column circuit suitable for accessing data of a bit line selected by the bank enable signals and a column address during a read or write operation.
An operation method of a memory system which includes a memory controller and a memory module having a plurality of memory chips each including a plurality of banks, the operation method comprising:
- storing, by the memory chips, a row or column address of memory cells as repair information, the memory cells being determined to be weak cells or defective cells;
- generating, by the memory controller, a mapping signal based on the repair information stored in the memory chips of the memory module during an initialization period;
- rearranging, by the memory chips, the order of the banks based on the mapping signal;
- and
- simultaneously accessing the respective banks of the memory chips in the rearranged order based on the same command and address after the initialization period.
Dependencies are inferred from the claim text.