Phase change memory devices and systems having reduced voltage threshold drift and associated methods
AssigneeIntel Corporation
InventorMattia Robustelli
Life of this patent
Estimating the term…
Abstract
Phase change memory devices, systems, and associated methods are provided and described. Such devices, systems, and methods manage and reduce voltage threshold drift to increase read accuracy of phase change memory. A pre-read pulse can be delivered across a select device and a phase change material of a phase change memory cell to at least partially reset the voltage threshold drift of the select device while maintaining a program state of the phase change material.
Claims23
A phase change memory device, comprising:
- an array of phase change memory (PCM) cells coupled together by an array of word lines and an array of bit lines, each PCM cell further comprising:
- a select device (SD);
- a phase change material (PM) coupled to the SD, the PM having a program state;
- and
- circuitry coupled to the array of PCM cells, the circuitry configured to:
- select a PCM cell;
- and
- deliver a pre-read pulse across the SD and the PM of the PCM cell, wherein the pre-read pulse is configured to at least partially reset a threshold voltage (Vt) drift of the SD while maintaining the program state of the PM.
A method of managing threshold voltage (Vt) drift in a phase change memory (PCM) cell, comprising:
- selecting a PCM cell, the PCM cell comprising a select device (SD) functionally coupled to a phase change material (PM) having a program state;
- and
- delivering a pre-read pulse across the SD and the PM of the PCM cell, wherein the pre-read pulse is configured to at least partially reset a Vt drift of the SD while maintaining the program state of the PM.
A computing system, comprising:
- at least one processor;
- a memory controller coupled to the processor;
- a memory array of phase change memory (PCM) cells each having:
- a select device (SD);
- and
- a phase change material (PM) having a program state and coupled to the SD;
- a plurality of metallization word lines coupled to groups of PCM cells across the PCM cell array and to the memory controller;
- a plurality of metallization bit lines coupled to groups of PCM cells across the PCM cell array and to the memory controller, wherein each PCM cell is uniquely addressed in the PCM cell array by a combination of word lines and bit lines;
- and
- circuitry coupled to the memory array and configured to:
- select a PCM cell;
- and
- deliver a pre-read pulse across the SD and the PM of the PCM cell, wherein the pre-read pulse is configured to at least partially reset a threshold voltage (Vt) drift of the SD while maintaining the program state of the PM.
Dependencies are inferred from the claim text.