CPU of PLC, system program for PLC, and recording medium storing system program for PLC
AssigneeOMRON Corporation
InventorsYoshihide Nishiyama, Osamu Hamasaki, Shigeyuki Eguchi, Yoshihide Tamura
Life of this patent
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Abstract
A scheduler causes a microprocessor to start execution of a first control program after a communication circuit transmits output data and receives input data in a control cycle following a control circle in which execution of the first control program has ended, and causes execution of an unexecuted portion of the first control program in a control cycle following a control cycle in which execution of the first control cycle has not ended.
Claims14
A central processing unit (CPU) of a programmable logic controller (PLC), the CPU comprising:
- a microprocessor that executes a first control program and a scheduler program, the first control program, when executed by the microprocessor, generates output data using input data, and the scheduler program, when executed by the microprocessor, controls execution of the first control program;
- a memory that stores the first control program and the scheduler program;
- a setting unit that determines a period of a control cycle;
- and
- a communication circuit that transmits the output data and receives the input data for every control cycle;
- the scheduler program, when executed by the microprocessor,
- causes the microprocessor to start execution of the first control program after the communication circuit transmits the output data and receives the input data, in a control cycle following a control cycle in which the first control program has ended;
- and
- causes the microprocessor to execute an unexecuted portion of the first control program in a control cycle following a control cycle in which the first control program has not ended,
- wherein the CPU is configured to control a control target of the PLC by repeating transmission of the output data, reception of the input data, and execution of the first control program.
A system for controlling programmable logic controller (PLC) comprising:
- a memory that stores executable instructions;
- a microprocessor of a central processing unit (CPU) that executes the executable instructions;
- and
- a communication circuit configured to transmit output data and receive input data, wherein the CPU controls a control target by repeating, for each control cycle, transmission of the output data and reception of the input data with the communication circuit, and by repeating execution of a first control program which is stored in the memory and generates the output data using the input data,
- wherein a scheduler controls execution of the first control program;
- and
- a setting unit sets a period of a control cycle,
- wherein the scheduler causes the microprocessor to start execution of the first control program after the communication circuit transmits the output data and receives the input data, in a control cycle following a control cycle in which the first control program has ended execution, and
- wherein the scheduler causes the microprocessor to execute an unexecuted portion of the first control program in a control cycle following a control cycle in which the first control program has not ended execution.
A non-transitory computer readable storage medium encoded with an executable computer program for a PLC and that, when executed by a microprocessor, causes the microprocessor to perform operations comprising:
- transmitting output data and receiving input data via a communication circuit;
- controlling a control target by repeating, for each control cycle, transmission of the output data and reception of the input data with the communication circuit, and by repeating execution of a first control program that generates the output data using the input data;
- controlling execution of the first control program;
- setting a period of a control cycle;
- starting execution of the first control program after the communication circuit transmits the output data and receives the input data, in a control cycle following a control cycle in which the first control program has ended execution;
- and
- executing an unexecuted portion of the first control program in a control cycle following a control cycle in which the first control program has not ended execution.
Dependencies are inferred from the claim text.