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US 9,614,564 B2Granted
High speed receivers circuits and methods
AssigneeIntel Corporation
InventorsKevin Chang, Stefano Giaconi
Life of this patent
Estimating the term…
Abstract
The present invention provides GPA embodiments. In some embodiments, a GPA stage with a negative capacitance unit is provided.
Claims26
An apparatus comprising:
- a differential amplifier having a first transistor with a gate terminal to receive a first input signal, and a second transistor with a gate terminal to receive a second input signal;
- an offset cancellation circuit coupled to the differential amplifier;
- and
- a negative impedance circuit having a third transistor with a gate terminal coupled to a drain terminal of the first transistor, and a fourth transistor with a gate terminal coupled to the drain terminal of the second transistor.
1 more element
An apparatus comprising:
- a first stage including a differential amplifier coupled to an offset cancellation circuit;
- a second stage coupled to the first stage, the second stage to reduce parasitic capacitance of one or more nodes of the first stage;
- and
- a third stage coupled to the second stage, wherein the third stage includes an amplifier.
1 more element
A method to improve gain, the method comprising:
- receiving a differential input signal by a differential amplifier;
- cancelling offset of the differential amplifier;
- and
- reducing parasitic at one or more nodes of the differential amplifier by a negative impedance circuit.
1 more element
An apparatus comprising:
- a differential amplifier having an offset cancellation circuit;
- a negative impedance circuit to reduce parasitic capacitance of one or more nodes of the differential amplifier;
- and
- an amplifier coupled to the negative impedance circuit.
1 more element
A computing platform, comprising:
- a first integrated circuit (IC) having a transmitter to send a bit stream;
- a transmission media;
- and
- a second IC coupled to the first IC via the transmission media, the second IC from a second IC having a receiver which is to receive the bit stream, wherein the bit stream is to provide a first input signal and a second input signal, and wherein the receiver comprises:
- a differential amplifier having an offset cancellation circuit and first and second transistors with corresponding gate terminals to receive the first and second input signals;
- a negative impedance circuit to reduce parasitic capacitance of one or more nodes of the differential amplifier;
- and
- an amplifier coupled to the negative impedance circuit.
5 more elements
Dependencies are inferred from the claim text.