Integrated circuit chip using top post-passivation technology and bottom structure technology
AssigneeQUALCOMM Incorporated
InventorsMou-Shiung Lin, Jin-Yuan Lee, Hsin-Jung Lo, Ping-Jung Yang, Te-Sheng Liu
Life of this patent
Estimating the term…
Abstract
Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.
Claims20
A processor unit comprising:
- a first cache memory chip coupled to a processor chip, in which the first cache memory chip is coupled to the processor chip through a plurality of micro interconnects between the first cache memory chip and the processor chip, wherein a pitch between a neighboring two of the plurality of micro interconnects is less than 60 micrometers;
- a substrate, in which the processor unit is on the substrate;
- and
- a mass storage on the substrate, wherein the mass storage comprises a first memory chip and a second memory chip coupled to the first memory chip, wherein the first memory chip is coupled to the second memory chip through at least one first wire bonded wire.
A processor unit, comprising:
- a first cache memory chip coupled to a processor chip, in which the first cache memory chip is coupled to the processor chip through a plurality of micro interconnects between the first cache memory chip and the processor chip, wherein a pitch between a neighboring two of the plurality of micro interconnects is less than 60 micrometers;
- a substrate, in which the processor unit is on the substrate;
- a mass storage on the substrate, wherein the mass storage comprises a first memory chip and a second memory chip coupled to the first memory chip, wherein the first memory chip is coupled to the second memory chip through at least one first wire bonded wire;
- a main memory on the substrate, wherein the main memory comprises a first dynamic-random-access-memory chip and a second dynamic-random-access-memory chip coupled to the first dynamic-random-access-memory chip;
- and
- an interconnect coupled to the substrate to form a module.
Dependencies are inferred from the claim text.