Methods and apparatus for reducing timing-skew errors in time-interleaved analog-to-digital converters

An analog-to-digital converter (ADC) apparatus, comprising:

• a flash ADC channel to sample an input analog signal according to a first clock signal having a first frequency, the flash ADC channel comprising:
• a first sampling switch to receive the first clock signal and to sample the input analog signal at a first sampling rate corresponding to the first frequency of the first clock signal so as to provide a first sampled input signal;
• a flash ADC coupled to the first sampling switch to receive the first sampled input signal and to provide a flash digital output corresponding to the first sampled input signal, the flash digital output constituting a timing reference for the ADC apparatus;
• a plurality of time-interleaved (TI) successive-approximation-register (SAR) ADC channels to respectively sample the input analog signal, each of the TI SAR ADC channels controlled by a corresponding TI clock signal to sample the input analog signal, the plurality of TI SAR ADC channels comprising:
• a plurality of additional sampling switches comprising at least a second sampling switch to receive a second clock signal and to sample the input analog signal at a second sampling rate corresponding to a second frequency of the second clock signal, so as to provide a second sampled input signal, wherein the second frequency of the second clock signal is less than the first frequency of the first clock signal;
• a plurality of TI SAR ADCs respectively coupled to the plurality of additional sampling switches, the plurality of TI SAR ADCs comprising at least a first TI SAR ADC coupled to the second sampling switch to receive the second sampled input signal and coupled to the flash ADC so as to receive the flash digital output, to
• provide a first TI digital output corresponding to the second sampled input signal and the flash digital output, wherein:
• the first TI digital output includes a plurality of most significant bits (MSBs) and a plurality of least significant bits (LSBs);
• and
• the plurality of MSBs of the first TI digital output are based on the flash digital output;
• a timing-skew controller coupled to the flash ADC channel and the plurality of TI SAR ADC channels to calculate a first variance of at least a portion of the first TI digital output provided by the first TI SAR ADC, based at least in part on the flash digital output constituting the timing reference, and thereby generate at least one first delay control signal;
• and
• a clock generator controller, coupled to at least the timing-skew controller, to receive the at least one first delay control signal from the timing-skew controller and a master clock signal, generate the first clock signal and the second clock signal based at least in part on the master clock signal, and variably adjust the second clock signal in time, with respect to the first clock signal, based on the at least one first delay control signal, so as to facilitate background timing-skew calibration of the ADC apparatus without interrupting normal operation of the ADC apparatus.

An analog-to-digital converter (ADC) apparatus, comprising:

• a plurality of time-interleaved (TI) ADC channels to respectively sample an input analog signal, each of the TI ADC channels controlled by a corresponding TI clock signal to sample the input analog signal;
• and
• a timing-skew controller coupled to the plurality of TI ADC channels to variably control a delay of at least one corresponding TI clock signal so as to facilitate background timing-skew calibration of the ADC apparatus without interrupting normal operation of the ADC apparatus,
• wherein the ADC apparatus does not include a separate TI ADC channel of the plurality of TI ADC channels as a timing reference channel to facilitate the background timing-skew calibration.

An analog-to-digital converter (ADC) apparatus, comprising:

• a coarse ADC channel to sample an input analog signal according to a first clock signal having a first frequency, the coarse ADC channel providing a coarse digital output corresponding to a sampled input analog signal at the first frequency and constituting a timing reference for the ADC apparatus;
• and
• a plurality of time-interleaved (TI) ADC channels to respectively sample the input analog signal, each of the TI ADC channels controlled by a corresponding TI clock signal to sample the input analog signal, each corresponding TI clock signal having a TI clock signal frequency that is lower than the first frequency of the first clock signal, wherein:
• a delay of at least one corresponding TI clock signal is variably controlled based at least in part on the coarse digital output constituting the timing reference for the ADC apparatus so as to facilitate background timing-skew calibration of the ADC apparatus without interrupting normal operation of the ADC apparatus;
• and
• the ADC apparatus does not include a separate timing reference TI ADC channel to facilitate the background timing-skew calibration.

A method for converting an input analog signal to a digital output, the method comprising:

• A) sampling the input analog signal according to a first clock signal having a first frequency to provide a coarse digital output corresponding to a sampled input analog signal at the first frequency and constituting a timing reference for the ADC apparatus;
• B) respectively sampling the input analog signal via a plurality of time-interleaved (TI) channels according to a plurality of corresponding TI clock signals, each corresponding TI clock signal having a TI clock signal frequency that is lower than the first frequency of the first clock signal;
• and
• C) variably controlling a delay of at least one corresponding TI clock signal based at least in part on the coarse digital output constituting the timing reference for the ADC apparatus so as to facilitate background timing-skew calibration of the ADC apparatus without interrupting normal operation of the ADC apparatus,
• wherein the plurality of TI channels does not include a separate timing reference TI channel to facilitate the background timing-skew calibration.