FINFETs with wrap-around silicide and method forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang, Ying-Keung Leung
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Abstract
A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
Claims20
A device comprising:
- isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width;
- a source/drain region having a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width, and the upper portion of the source/drain region has substantially vertical sidewalls;
- a source/drain silicide region with inner sidewalls contacting the vertical sidewalls of the source/drain region;
- and
- a dielectric etch stop layer comprising:
- a horizontal portion having a bottom surface contacting a top surface of the isolation regions;
- and
- a vertical portion comprising a bottom end connected to an end of the horizontal portion, wherein the source/drain region comprises a sidewall contacting an inner sidewall of the vertical portion of the dielectric etch stop layer.
A device comprising:
- Shallow Trench Isolation (STI) regions;
- a semiconductor strip between opposite portions of the STI regions;
- an oxide region overlapping the semiconductor strip;
- and
- a source/drain region overlapping the oxide region, the source/drain region comprising:
- a lower portion, wherein respective edges of the semiconductor strip, the oxide region, and the source/drain region are substantially aligned;
- and
- an upper portion over the lower portion, wherein the upper portion comprises substantially vertical sidewalls, and the upper portion extends laterally beyond respective edges of the lower portion.
A device comprising:
- Shallow Trench Isolation (STI) regions;
- a semiconductor strip between opposite portions of the STI regions;
- a source/drain region comprising:
- a lower portion overlapping the semiconductor strip;
- and
- an upper portion overlapping the lower portion, wherein the upper portion comprises substantially vertical sidewalls, and the upper portion extends laterally beyond respective edges of the lower portion;
- a dielectric etch stop layer comprising portions contacting opposite vertical sidewalls of the lower portion of the source/drain region;
- and
- a silicide region comprising portions contacting the substantially vertical sidewalls of the upper portion of the source/drain region.
Dependencies are inferred from the claim text.